| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| H A D | Thumb2RegisterInfo.cpp | 34 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
|
| H A D | Thumb2InstrInfo.cpp | 62 unsigned PredReg = 0; local
110 unsigned PredReg = 0; local
213 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
[all...] |
| H A D | Thumb1RegisterInfo.cpp | 64 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
|
| H A D | Thumb2ITBlockPass.cpp | 170 unsigned PredReg = 0; local
|
| H A D | MLxExpansionPass.cpp | 284 unsigned PredReg = MI->getOperand(++NextOp).getReg(); local
|
| H A D | ARMBaseRegisterInfo.cpp | 750 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); local
391 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
|
| H A D | ARMExpandPseudoInsts.cpp | 617 unsigned PredReg = 0; local
|
| H A D | Thumb2SizeReduction.cpp | 583 unsigned PredReg = 0; local
687 unsigned PredReg = 0; local
784 unsigned PredReg = 0; local
|
| H A D | ARMFrameLowering.cpp | 1432 unsigned PredReg = Old->getOperand(2).getReg(); local
1437 unsigned PredReg local
[all...] |
| H A D | ARMConstantIslandPass.cpp | 1350 unsigned PredReg = 0; local
1796 unsigned PredReg = 0; local
|
| H A D | ARMLoadStoreOptimizer.cpp | 286 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument
425 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument
523 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument
609 isMatchingDecrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument
642 isMatchingIncrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument
798 unsigned PredReg = 0; local
951 unsigned PredReg = 0; local
1152 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1209 unsigned PredReg = 0; local
1328 unsigned PredReg = 0; local
1655 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument
1821 unsigned BaseReg = 0, PredReg = 0; local
1918 unsigned PredReg = 0; local
[all...] |
| H A D | ARMISelDAGToDAG.cpp | 2504 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local
2767 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local
2787 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local
2806 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local
|
| H A D | ARMBaseInstrInfo.cpp | 1619 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { argument
1649 unsigned PredReg = 0; local
1824 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
|
| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 500 unsigned PredReg = Cond[Cond.size()-1].getReg(); local
|