Target/ARM/ARMLoadStoreOptimizer.cpp

99                   ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
113                         unsigned PredReg,
119                       ARMCC::CondCodes Pred, unsigned PredReg,
290                           unsigned PredReg, unsigned Scratch, DebugLoc dl,
344       .addImm(Pred).addReg(PredReg).addReg(0);
355     .addImm(Pred).addReg(PredReg);
431                                      ARMCC::CondCodes Pred, unsigned PredReg,
483                 Pred, PredReg, Scratch, dl, Regs, ImpDefs))
525                          ARMCC::CondCodes Pred, unsigned PredReg,
579                      Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
580       MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
591                  Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
611                                 ARMCC::CondCodes Pred, unsigned PredReg) {
636         MyPredReg == PredReg))
644                                 ARMCC::CondCodes Pred, unsigned PredReg) {
669         MyPredReg == PredReg))
798   unsigned PredReg = 0;
799   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
819         isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
823                isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
838         isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
841                isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
860     .addImm(Pred).addReg(PredReg);
951   unsigned PredReg = 0;
952   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
965     if (isMatchingDecrement(PrevMBBI, Base, Bytes, Limit, Pred, PredReg)) {
969                isMatchingIncrement(PrevMBBI, Base, Bytes, Limit,Pred,PredReg)) {
985         isMatchingDecrement(NextMBBI, Base, Bytes, Limit, Pred, PredReg)) {
988     } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Limit,Pred,PredReg)) {
1013       .addImm(Pred).addReg(PredReg)
1023           .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1028           .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
1035         .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1047         .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
1053         .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1159                           ARMCC::CondCodes Pred, unsigned PredReg,
1166     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1172     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1209     unsigned PredReg = 0;
1210     ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1221           .addImm(Pred).addReg(PredReg)
1228           .addImm(Pred).addReg(PredReg)
1256                       Pred, PredReg, TII, isT2);
1261                       Pred, PredReg, TII, isT2);
1276                       Pred, PredReg, TII, isT2);
1281                       Pred, PredReg, TII, isT2);
1328       unsigned PredReg = 0;
1329       ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
1363         CurrPredReg = PredReg;
1374           // No need to match PredReg.
1564                           unsigned &PredReg, ARMCC::CondCodes &Pred,
1659                                           int &Offset, unsigned &PredReg,
1722   Pred = getInstrPredicate(Op0, PredReg);
1821         unsigned BaseReg = 0, PredReg = 0;
1829                                              Offset, PredReg, Pred, isT2)) {
1849             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1863             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1918       unsigned PredReg = 0;
1919       if (getInstrPredicate(MI, PredReg) != ARMCC::AL)