| /freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.h | 30 ArrayRef<MCPhysReg> Order; member in class:llvm::AllocationOrder
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| H A D | CriticalAntiDepBreaker.cpp | 366 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); local
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| H A D | TargetRegisterInfo.cpp | 133 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); local
264 getRegAllocationHints(unsigned VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM) const argument
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| H A D | RegAllocGreedy.cpp | 456 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
681 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, unsigned CostPerUseLimit) argument
1172 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
1307 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
1359 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
1493 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
[all...] |
| /freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 34 OwningArrayPtr<MCPhysReg> Order; member in struct:llvm::RegisterClassInfo::RCInfo
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| H A D | ScheduleDAG.h | 52 Order ///< Any other ordering dependency. enumerator in enum:llvm::SDep::Kind
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| H A D | SelectionDAGNodes.h | 428 void setIROrder(unsigned Order) { IROrder = Order; } argument
906 UnarySDNode(unsigned Opc, unsigned Order, DebugLo argument
918 BinarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y) argument
930 TernarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y, SDValue Z) argument
1109 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
1118 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
1127 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
1136 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue* AllOps, SDUse *DynOps, unsigned NumOps, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
1180 MemIntrinsicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, const SDValue *Ops, unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO) argument
1213 ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, SDValue N1, SDValue N2, const int *M) argument
1587 EHLabelSDNode(unsigned Order, DebugLoc dl, SDValue ch, MCSymbol *L) argument
1640 CvtRndSatSDNode(EVT VT, unsigned Order, DebugLoc dl, const SDValue *Ops, unsigned NumOps, ISD::CvtCode Code) argument
1684 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, DebugLoc dl, SDValue *Operands, unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument
1722 LoadSDNode(SDValue *ChainPtrOff, unsigned Order, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument
1751 StoreSDNode(SDValue *ChainValuePtrOff, unsigned Order, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument
1787 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc DL, SDVTList VTs) argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 50 unsigned Order; member in class:llvm::SDDbgValue
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| H A D | SelectionDAGDumper.cpp | 499 OS << " [ORD=" << Order << ']'; local
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| H A D | SelectionDAG.cpp | 5316 unsigned Order = std::min(N->getIROrder(), OLoc.getIROrder()); local
6054 GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, unsigned Order, argument
6061 AddrSpaceCastSDNode::AddrSpaceCastSDNode(unsigned Order, DebugLoc dl, EVT VT, argument
6067 MemSDNode::MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, argument
6078 MemSDNode::MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Support/ |
| H A D | Dwarf.cpp | 624 const char *llvm::dwarf::ArrayOrderString(unsigned Order) { argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 210 getRegAllocationHints(unsigned VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM) const argument
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| /freebsd-10-stable/contrib/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 854 ArrayRef<Record*> Order = RC.getOrder(); local
1033 ArrayRef<Record*> Order = RC.getOrder(); local
[all...] |
| H A D | CodeGenRegisters.h | 437 unsigned Order; // Cache the sort key. member in struct:llvm::RegUnitSet
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| H A D | CodeGenRegisters.cpp | 697 SetTheory::RecSet Order; local
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/MC/ |
| H A D | MachObjectWriter.cpp | 607 const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder(); local
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| /freebsd-10-stable/contrib/llvm/lib/Transforms/Scalar/ |
| H A D | StructurizeCFG.cpp | 169 RNVector Order; member in class:__anon2830::StructurizeCFG
[all...] |
| /freebsd-10-stable/contrib/llvm/tools/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 354 llvm::Value *Ptr, *Order, *OrderFail = 0, *Val1 = 0, *Val2 = 0; local
188 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, llvm::Value *Dest, llvm::Value *Ptr, llvm::Value *Val1, llvm::Value *Val2, uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) argument
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| H A D | CGBuiltin.cpp | 1079 Value *Order = EmitScalarExpr(E->getArg(1)); local
1165 Value *Order = EmitScalarExpr(E->getArg(1)); local
1225 Value *Order = EmitScalarExpr(E->getArg(0)); local
[all...] |
| /freebsd-10-stable/usr.bin/make/ |
| H A D | parse.c | 166 Order, /* .ORDER */ enumerator in enum:__anon11969
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| /freebsd-10-stable/sys/contrib/dev/acpica/include/ |
| H A D | acbuffer.h | 144 UINT8 Order; member in struct:acpi_pld_info
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1392 bool Order = orderBumpCompare(BumpI, PredDef); local
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| /freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXAsmPrinter.cpp | 82 VisitGlobalVariableForEmission( const GlobalVariable *GV, SmallVectorImpl<const GlobalVariable *> &Order, DenseSet<const GlobalVariable *> &Visited, DenseSet<const GlobalVariable *> &Visiting) argument
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| /freebsd-10-stable/contrib/bmake/ |
| H A D | parse.c | 210 Order, /* .ORDER */ enumerator in enum:__anon72
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| /freebsd-10-stable/contrib/llvm/lib/IR/ |
| H A D | Instructions.cpp | 997 LoadInst(Value *Ptr, const Twine &Name, bool isVolatile, unsigned Align, AtomicOrdering Order, SynchronizationScope SynchScope, Instruction *InsertBef) argument
1010 LoadInst(Value *Ptr, const Twine &Name, bool isVolatile, unsigned Align, AtomicOrdering Order, SynchronizationScope SynchScope, BasicBlock *InsertAE) argument
1144 StoreInst(Value *val, Value *addr, bool isVolatile, unsigned Align, AtomicOrdering Order, SynchronizationScope SynchScope, Instruction *InsertBefore) argument
1188 StoreInst(Value *val, Value *addr, bool isVolatile, unsigned Align, AtomicOrdering Order, SynchronizationScope SynchScope, BasicBlock *InsertAtEnd) argument
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