/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Support/ |
H A D | GetElementPtrTypeIterator.h | 102 gep_type_begin(Type *Op0, ArrayRef<T> A) { argument 108 gep_type_end(Type *Op0, ArrayRef<T> A) { argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 224 MachineOperand &Op0 = MI->getOperand(0); local
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H A D | HexagonISelDAGToDAG.cpp | 1494 SDValue Op0, Op1; local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 192 SDValue Op0, Op1; local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/Scalar/ |
H A D | CorrelatedValuePropagation.cpp | 144 Value *Op0 = C->getOperand(0); local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/VMCore/ |
H A D | AutoUpgrade.cpp | 271 Value *Op0 = CI->getArgOperand(0); local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 288 SDValue Op0, Op1; local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/InstCombine/ |
H A D | InstCombineAddSub.cpp | 496 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 654 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineMulDivRem.cpp | 101 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 257 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 367 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 432 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 518 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 571 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 596 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 628 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 671 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 742 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1, argument [all...] |
H A D | InstCombineCalls.cpp | 590 Value *Op0 = Builder->CreateBitCast(II->getArgOperand(0), local
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H A D | InstCombineAndOrXor.cpp | 720 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 1019 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1448 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 1721 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2044 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2257 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local [all...] |
H A D | InstCombineCasts.cpp | 883 Value *Op0 = ICI->getOperand(0), *Op1 = ICI->getOperand(1); local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 643 SDValue Op0, Op1; local
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 585 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 603 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Analysis/ |
H A D | ConstantFolding.cpp | 545 static Constant *SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0, argument
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H A D | ValueTracking.cpp | 46 static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW, argument 132 static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW, argument 1225 Value *Op0 = I->getOperand(0); local [all...] |
H A D | InstructionSimplify.cpp | 592 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 653 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 757 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 882 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 891 SimplifyMulInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 954 SimplifyMulInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 962 SimplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1034 SimplifySDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1042 SimplifySDivInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1050 SimplifyUDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1058 SimplifyUDivInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1064 SimplifyFDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned) argument 1077 SimplifyFDivInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1085 SimplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1139 SimplifySRemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1147 SimplifySRemInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1155 SimplifyURemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1163 SimplifyURemInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1169 SimplifyFRemInst(Value *Op0, Value *Op1, const Query &, unsigned) argument 1182 SimplifyFRemInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1190 SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1234 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 1250 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1259 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1277 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1287 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1309 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1319 SimplifyAndInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1410 SimplifyAndInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1418 SimplifyOrInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1504 SimplifyOrInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1512 SimplifyXorInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1564 SimplifyXorInst(Value *Op0, Value *Op1, const TargetData *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 381 unsigned Op0 = getRegForValue(I->getOperand(0)); local 749 unsigned Op0 = getRegForValue(I->getOperand(0)); local 913 const Value *Op0 local 1124 FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument 1173 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 1192 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 1213 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 1237 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 1258 FastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument 1281 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument 1302 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1326 FastEmitInst_rrii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm1, uint64_t Imm2) argument 1383 FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument 1399 FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/ExecutionEngine/ |
H A D | ExecutionEngine.cpp | 554 Constant *Op0 = CE->getOperand(0); local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/ |
H A D | SPUISelDAGToDAG.cpp | 266 SDValue Op0, Op1; local 343 SDValue Op0 local 417 const SDValue Op0 = N.getOperand(0); local 470 const SDValue Op0 = N.getOperand(0); local 641 SDValue Op0 = N->getOperand(0); local 741 SDValue Op0 = N->getOperand(0); local 789 SDValue Op0 = N->getOperand(0); local 852 SDValue Op0 = N->getOperand(0); local 903 SDValue Op0 = N->getOperand(0); local 971 SDValue Op0 = N->getOperand(0); local 1129 SDValue Op0 = i64vec.getOperand(0); local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 392 SDValue Op0 = N->getOperand(0); local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 300 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 319 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 341 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 366 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 388 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument 410 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 474 FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument 1215 Value *Op0 = I->getOperand(0); local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 1544 static void concatenateMemOperands(MachineInstr *MI, MachineInstr *Op0, argument 1560 ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, argument 1722 MachineInstr *Op0 = Ops.back(); local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86FastISel.cpp | 891 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, argument 989 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); local 1089 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); local [all...] |