Searched defs:DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT (Results 1 - 1 of 1) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h1124 #define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse macro

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