1/* $NetBSD: irqsrcs_dcn_1_0.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3/* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28#ifndef __IRQSRCS_DCN_1_0_H__ 29#define __IRQSRCS_DCN_1_0_H__ 30 31 32#define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 33#define DCN_1_0__CTXID__DC_I2C_SW_DONE 0 34 35#define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 36#define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1 37 38#define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 39#define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2 40 41#define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 42#define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3 43 44#define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 45#define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 46 47#define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 48#define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5 49 50#define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 51#define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6 52 53#define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 54#define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7 55 56#define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 57#define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8 58 59#define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 60#define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9 61 62#define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 63#define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10 64 65#define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 66#define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11 67 68#define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 69#define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12 70 71#define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 72#define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13 73 74#define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 75#define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14 76 77#define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 78#define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15 79 80#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 81#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7 82 83#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 84#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8 85 86#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 87#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7 88 89#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 90#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8 91 92#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 93#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7 94 95#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 96#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8 97 98#define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level 99#define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12 100 101#define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level 102#define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13 103 104#define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level 105#define DCN_1_0__CTXID__DMCU_SCP_INT 14 106 107#define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 108#define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0 109 110#define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 111#define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1 112 113#define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 114#define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2 115 116#define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level 117#define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3 118 119#define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level 120#define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4 121 122#define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level 123#define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5 124 125#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 126#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6 127 128#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 129#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7 130 131#define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 132#define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1 133 134#define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 135#define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0 136 137#define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 138#define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1 139 140#define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 141#define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2 142 143#define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 144#define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3 145 146#define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 147#define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4 148 149#define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 150#define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5 151 152#define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 153#define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6 154 155#define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 156#define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7 157 158#define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level 159#define DCN_1_0__CTXID__DC_HPD1_INT 0 160 161#define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 162#define DCN_1_0__CTXID__DC_HPD2_INT 1 163 164#define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 165#define DCN_1_0__CTXID__DC_HPD3_INT 2 166 167#define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 168#define DCN_1_0__CTXID__DC_HPD4_INT 3 169 170#define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 171#define DCN_1_0__CTXID__DC_HPD5_INT 4 172 173#define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 174#define DCN_1_0__CTXID__DC_HPD6_INT 5 175 176#define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level 177#define DCN_1_0__CTXID__DC_HPD1_RX_INT 6 178 179#define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 180#define DCN_1_0__CTXID__DC_HPD2_RX_INT 7 181 182#define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 183#define DCN_1_0__CTXID__DC_HPD3_RX_INT 8 184 185#define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 186#define DCN_1_0__CTXID__DC_HPD4_RX_INT 9 187 188#define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 189#define DCN_1_0__CTXID__DC_HPD5_RX_INT 10 190 191#define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 192#define DCN_1_0__CTXID__DC_HPD6_RX_INT 11 193 194#define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level 195#define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0 196 197#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 198#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2 199 200#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 201#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3 202 203#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 204#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4 205 206#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 207#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5 208 209#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 210#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6 211 212#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 213#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7 214 215#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 216#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8 217 218#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 219#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9 220 221#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 222#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0 223 224#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 225#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1 226 227#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 228#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2 229 230#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 231#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3 232 233#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 234#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4 235 236#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 237#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5 238 239#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 240#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6 241 242#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 243#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7 244 245#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 246#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0 247 248#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 249#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1 250 251#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 252#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2 253 254#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 255#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3 256 257#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 258#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4 259 260#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 261#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5 262 263#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 264#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6 265 266#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 267#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7 268 269#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 270#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0 271 272#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 273#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1 274 275#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 276#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2 277 278#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 279#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3 280 281#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 282#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4 283 284#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 285#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5 286 287#define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level 288#define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0 289 290#define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 291#define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1 292 293#define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 294#define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2 295 296#define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 297#define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3 298 299#define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 300#define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4 301 302#define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 303#define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5 304 305#define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level 306#define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6 307 308#define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 309#define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7 310 311#define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level 312#define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0 313 314#define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 315#define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1 316 317#define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 318#define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2 319 320#define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 321#define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3 322 323#define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 324#define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4 325 326#define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 327#define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5 328 329#define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level 330#define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6 331 332#define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 333#define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7 334 335#define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 336#define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0 337 338#define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 339#define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1 340 341#define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 342#define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2 343 344#define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 345#define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3 346 347#define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 348#define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4 349 350#define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 351#define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5 352 353#define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 354#define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6 355 356#define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 357#define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7 358 359#define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 360#define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8 361 362#define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 363#define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9 364 365#define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 366#define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10 367 368#define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 369#define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11 370 371#define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 372#define DCN_1_0__CTXID__VGA_CRT_INT 12 373 374#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 375#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0 376 377#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level 378#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1 379 380#define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 381#define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0 382 383#define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 384#define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1 385 386#define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 387#define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2 388 389#define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 390#define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3 391 392#define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 393#define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4 394 395#define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 396#define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5 397 398#define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 399#define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6 400 401#define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 402#define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7 403 404#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 405#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0 406 407#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 408#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1 409 410#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 411#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2 412 413#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 414#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3 415 416#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 417#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4 418 419#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 420#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5 421 422#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 423#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0 424 425#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 426#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1 427 428#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 429#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2 430 431#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 432#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3 433 434#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 435#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4 436 437#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 438#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5 439 440#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 441#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6 442 443#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 444#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7 445 446#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 447#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8 448 449#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 450#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9 451 452#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 453#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10 454 455#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 456#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11 457 458#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 459#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12 460 461#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 462#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13 463 464#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 465#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14 466 467#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 468#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15 469 470#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 471#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0 472 473#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 474#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1 475 476#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 477#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2 478 479#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 480#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3 481 482#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 483#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4 484 485#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 486#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5 487 488#define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level 489#define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6 490 491#define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 492#define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7 493 494#define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 495#define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8 496 497#define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 498#define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9 499 500#define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 501#define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10 502 503#define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 504#define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11 505 506#define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 507#define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0 508 509#define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 510#define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1 511 512#define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 513#define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2 514 515#define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 516#define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3 517 518#define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 519#define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4 520 521#define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 522#define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5 523 524#define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 525#define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6 526 527#define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 528#define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7 529 530#define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 531#define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0 532 533#define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 534#define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1 535 536#define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 537#define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2 538 539#define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 540#define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3 541 542#define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 543#define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4 544 545#define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 546#define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5 547 548#define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 549#define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6 550 551#define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 552#define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7 553 554#define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 555#define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8 556 557#define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 558#define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9 559 560#define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 561#define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10 562 563#define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 564#define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11 565 566#define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 567#define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE 0x19 // D2 : OTG V_update OTG2_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 568#define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 569#define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE 0x1B // D4 : OTG V_update OTG4_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 570#define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 571#define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 572 573#define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 574#define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0 575 576#define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 577#define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1 578 579#define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 580#define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2 581 582#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 583#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3 584 585#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 586#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4 587 588#define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 589#define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5 590 591#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 592#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6 593 594#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 595#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7 596 597#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 598#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8 599 600#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 601#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 602 603#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 604#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 605 606#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 607#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 608 609#define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse 610#define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12 611 612#define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 613#define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0 614 615#define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 616#define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1 617 618#define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 619#define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2 620 621#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 622#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3 623 624#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 625#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4 626 627#define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 628#define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5 629 630#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 631#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6 632 633#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 634#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7 635 636#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 637#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8 638 639#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 640#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 641 642#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 643#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 644 645#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 646#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 647 648#define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 649#define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12 650 651#define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 652#define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0 653 654#define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 655#define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1 656 657#define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 658#define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2 659 660#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 661#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3 662 663#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 664#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4 665 666#define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 667#define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5 668 669#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 670#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6 671 672#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 673#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7 674 675#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 676#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8 677 678#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 679#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 680 681#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 682#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 683 684#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 685#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 686 687#define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 688#define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12 689 690#define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 691#define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0 692 693#define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 694#define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1 695 696#define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 697#define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2 698 699#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 700#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3 701 702#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 703#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4 704 705#define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 706#define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5 707 708#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 709#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6 710 711#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 712#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7 713 714#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 715#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8 716 717#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 718#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 719 720#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 721#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 722 723#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 724#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 725 726#define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 727#define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12 728 729#define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 730#define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0 731 732#define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 733#define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1 734 735#define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 736#define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2 737 738#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 739#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3 740 741#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 742#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4 743 744#define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 745#define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5 746 747#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 748#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6 749 750#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 751#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7 752 753#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 754#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8 755 756#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 757#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 758 759#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 760#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 761 762#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 763#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 764 765#define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 766#define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12 767 768#define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 769#define DCN_1_0__CTXID__DC_D1_VBLANK 0 770 771#define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 772#define DCN_1_0__CTXID__DC_D1_VLINE1 1 773 774#define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 775#define DCN_1_0__CTXID__DC_D1_VLINE2 2 776 777#define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 778#define DCN_1_0__CTXID__DC_D2_VBLANK 3 779 780#define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 781#define DCN_1_0__CTXID__DC_D2_VLINE1 4 782 783#define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 784#define DCN_1_0__CTXID__DC_D2_VLINE2 5 785 786#define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 787#define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6 788 789#define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 790#define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7 791 792#define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 793#define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8 794 795#define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 796#define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9 797 798#define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 799#define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10 800 801#define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 802#define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11 803 804#define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 805#define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12 806 807#define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 808#define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13 809 810#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 811#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0 812 813#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 814#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1 815 816#define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 817#define DCN_1_0__CTXID__DC_D3_VBLANK 9 818 819#define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 820#define DCN_1_0__CTXID__DC_D3_VLINE1 10 821 822#define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 823#define DCN_1_0__CTXID__DC_D3_VLINE2 11 824 825#define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 826#define DCN_1_0__CTXID__DC_D4_VBLANK 12 827 828#define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 829#define DCN_1_0__CTXID__DC_D4_VLINE1 13 830 831#define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 832#define DCN_1_0__CTXID__DC_D4_VLINE2 14 833 834#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 835#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0 836 837#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 838#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1 839 840#define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 841#define DCN_1_0__CTXID__DC_D5_VBLANK 9 842 843#define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 844#define DCN_1_0__CTXID__DC_D5_VLINE1 10 845 846#define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 847#define DCN_1_0__CTXID__DC_D5_VLINE2 11 848 849#define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 850#define DCN_1_0__CTXID__DC_D6_VBLANK 12 851 852#define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 853#define DCN_1_0__CTXID__DC_D6_VLINE1 13 854 855#define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 856#define DCN_1_0__CTXID__DC_D6_VLINE2 14 857 858#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 859#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0 860 861#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 862#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1 863 864#define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 865#define DCN_1_0__CTXID__DC_D7_VBLANK 9 866 867#define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 868#define DCN_1_0__CTXID__DC_D7_VLINE1 10 869 870#define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 871#define DCN_1_0__CTXID__DC_D7_VLINE2 11 872 873#define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 874#define DCN_1_0__CTXID__DC_D8_VBLANK 12 875 876#define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 877#define DCN_1_0__CTXID__DC_D8_VLINE1 13 878 879#define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 880#define DCN_1_0__CTXID__DC_D8_VLINE2 14 881 882#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 883#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0 884 885#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 886#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1 887 888#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 889#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0 890 891#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 892#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1 893 894#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 895#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0 896 897#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 898#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1 899 900#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 901#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0 902 903#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 904#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1 905 906#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 907#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0 908 909#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 910#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1 911 912#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 913#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0 914 915#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 916#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1 917 918#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 919#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0 920 921#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 922#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1 923 924#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 925#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0 926 927#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 928#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1 929 930#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 931#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0 932 933#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 934#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1 935 936#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 937#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0 938 939#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 940#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1 941 942#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 943#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0 944 945#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 946#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1 947 948#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 949#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0 950 951#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 952#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1 953 954#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 955#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0 956 957#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 958#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1 959 960#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse 961#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0 962 963#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 964#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1 965 966#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 967#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0 968 969#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 970#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1 971 972#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 973#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0 974 975#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 976#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1 977 978#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 979#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0 980 981#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 982#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1 983 984#define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 985#define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0 986 987#define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 988#define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1 989 990#define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 991#define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2 992 993#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 994#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3 995 996#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 997#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4 998 999#define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1000#define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5 1001 1002#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1003#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6 1004 1005#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1006#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7 1007 1008#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1009#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8 1010 1011#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1012#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 1013 1014#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1015#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 1016 1017#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1018#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 1019 1020#define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1021#define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12 1022 1023#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1024#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0 1025 1026#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 1027#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1 1028 1029#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1030#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0 1031 1032#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 1033#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1 1034 1035#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1036#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0 1037 1038#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 1039#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1 1040 1041#define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1042#define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP 0x3D // "OTG1 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG2_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1043#define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP 0x3E // "OTG2 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG3_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1044#define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP 0x3F // "OTG3 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG4_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1045#define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP 0x40 // "OTG4 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG5_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1046#define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP 0x41 // "OTG5 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG6_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1047 1048#define DCN_1_0__SRCID__DC_D1_OTG_VREADY 0x42 // "OTG0 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG1_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1049#define DCN_1_0__SRCID__DC_D2_OTG_VREADY 0x43 // "OTG1 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG2_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1050#define DCN_1_0__SRCID__DC_D3_OTG_VREADY 0x44 // "OTG2 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG3_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1051#define DCN_1_0__SRCID__DC_D4_OTG_VREADY 0x45 // "OTG3 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG4_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1052#define DCN_1_0__SRCID__DC_D5_OTG_VREADY 0x46 // "OTG4 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG5_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1053#define DCN_1_0__SRCID__DC_D6_OTG_VREADY 0x47 // "OTG5 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG6_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1054 1055#define DCN_1_0__SRCID__OTG0_VSYNC_NOM 0x48 // OTG0 vsync nom interrupt OTG1_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 1056#define DCN_1_0__SRCID__OTG1_VSYNC_NOM 0x49 // OTG1 vsync nom interrupt OTG2_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 1057#define DCN_1_0__SRCID__OTG2_VSYNC_NOM 0x4A // OTG2 vsync nom interrupt OTG3_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 1058#define DCN_1_0__SRCID__OTG3_VSYNC_NOM 0x4B // OTG3 vsync nom interrupt OTG4_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 1059#define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 1060#define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1061 1062#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1063#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0 1064 1065#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1066#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1 1067 1068#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1069#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2 1070 1071#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1072#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3 1073 1074#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1075#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4 1076 1077#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1078#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5 1079 1080#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1081#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6 1082 1083#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1084#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7 1085 1086#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1087#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8 1088 1089#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1090#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9 1091 1092#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1093#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10 1094 1095#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1096#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11 1097 1098#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1099#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12 1100 1101#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1102#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13 1103 1104#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1105#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14 1106 1107#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1108#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15 1109 1110#define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1111#define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT 0x50 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP1_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1112#define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT 0x51 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP2_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1113#define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT 0x52 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP3_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1114#define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT 0x53 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP4_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1115#define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT 0x54 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP5_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1116#define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT 0x55 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP6_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1117#define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT 0x56 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP7_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1118 1119#define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x57 // "OTG0 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1120#define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1121#define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x59 // "OTG2 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1122#define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1123#define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5B // "OTG4 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1124#define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1125 1126#define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT 0x5D // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP0_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1127#define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT 0x5E // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP1_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1128#define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT 0x5F // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP2_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1129#define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT 0x60 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP3_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1130#define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT 0x61 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP4_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1131#define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT 0x62 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP5_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1132#define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1133#define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1134 1135 1136#endif // __IRQSRCS_DCN_1_0_H__ 1137