| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFSelectionDAGInfo.cpp | 20 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGAddressAnalysis.h | 72 bool contains(const SelectionDAG &DAG, int64_t BitSize, argument
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| H A D | ScoreboardHazardRecognizer.h | 96 const ScheduleDAG *DAG; member in class:llvm::ScoreboardHazardRecognizer
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| H A D | SelectionDAGTargetInfo.h | 51 virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, argument
80 virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, argument
93 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, argument
105 EmitTargetCodeForMemchr(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, argument
118 EmitTargetCodeForStrcpy(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, argument
130 EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, argument
138 EmitTargetCodeForStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, argument
144 EmitTargetCodeForStrnlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, argument
150 virtual SDValue EmitTargetCodeForSetTag(SelectionDAG &DAG, cons argument
67 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCHazardRecognizers.h | 26 const ScheduleDAG *DAG; member in class:llvm::PPCDispatchGroupSBHazardRecognizer
56 const ScheduleDAG &DAG; member in class:llvm::PPCHazardRecognizer970
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| H A D | PPCHazardRecognizers.cpp | 262 PPCHazardRecognizer970::PPCHazardRecognizer970(const ScheduleDAG &DAG) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.h | 283 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const argument
290 CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const argument
[all...] |
| H A D | AMDGPUExportClustering.cpp | 59 static void buildCluster(ArrayRef<SUnit *> Exports, ScheduleDAGInstrs *DAG) { argument
82 static void removeExportDependencies(ScheduleDAGInstrs *DAG, SUnit &SU) { argument
108 void ExportClustering::apply(ScheduleDAGInstrs *DAG) { argument
[all...] |
| H A D | GCNMinRegStrategy.cpp | 225 schedule(ArrayRef<const SUnit*> TopRoots, const ScheduleDAG &DAG) argument
271 makeMinRegSchedule(ArrayRef<const SUnit*> TopRoots, const ScheduleDAG &DAG) argument
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| H A D | R600MachineScheduler.h | 28 const ScheduleDAGMILive *DAG = nullptr; member in class:llvm::final
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| H A D | GCNILPSched.cpp | 290 schedule(ArrayRef<const SUnit*> BotRoots, const ScheduleDAG &DAG) argument
357 makeGCNILPScheduler(ArrayRef<const SUnit*> BotRoots, const ScheduleDAG &DAG) argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreSelectionDAGInfo.cpp | 18 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.h | 49 SelectionDAG *DAG; // DAG of the current basic block member in class:llvm::ScheduleDAGSDNodes
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| H A D | SelectionDAGAddressAnalysis.cpp | 157 bool BaseIndexOffset::contains(const SelectionDAG &DAG, int64_t BitSize, argument
23 equalBaseIndex(const BaseIndexOffset &Other, const SelectionDAG &DAG, int64_t &Off) const argument
86 computeAliasing(const SDNode *Op0, const Optional<int64_t> NumBytes0, const SDNode *Op1, const Optional<int64_t> NumBytes1, const SelectionDAG &DAG, bool &IsAlias) argument
178 matchLSNode(const LSBaseSDNode *N, const SelectionDAG &DAG) argument
281 match(const SDNode *N, const SelectionDAG &DAG) argument
[all...] |
| H A D | ScheduleDAGSDNodes.cpp | 140 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs, argument
161 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { argument
186 RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MacroFusion.cpp | 54 static bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU, argument
154 apply(ScheduleDAGInstrs *DAG) argument
168 scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblySelectionDAGInfo.cpp | 21 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool IsVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
36 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool IsVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
45 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Val, SDValue Size, Align Alignment, bool IsVolatile, MachinePointerInfo DstPtrInfo) const argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSelectionDAGInfo.cpp | 19 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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| H A D | HexagonMachineScheduler.h | 134 VLIWMachineScheduler *DAG = nullptr; member in struct:llvm::ConvergingVLIWScheduler::VLIWSchedBoundary
217 VLIWMachineScheduler *DAG = nullptr; member in class:llvm::ConvergingVLIWScheduler
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| H A D | HexagonTargetMachine.cpp | 123 ScheduleDAGMILive *DAG = local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 378 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, argument
397 getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const argument
410 getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const argument
473 getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 341 ScheduleDAGMILive *DAG = createGenericSchedLive(C); variable
351 ScheduleDAGMI *DAG = createGenericSchedPostRA(C); variable
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| H A D | ARMSelectionDAGInfo.cpp | 38 EmitSpecializedLibcall( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, RTLIB::Libcall LC) const argument
142 shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, const SelectionDAG &DAG, ConstantSDNode *ConstantSize, Align Alignment, bool IsMemcpy) argument
169 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
289 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
297 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
[all...] |
| H A D | ARMHazardRecognizer.cpp | 165 ARMBankConflictHazardRecognizer( const ScheduleDAG *DAG, int64_t CPUBankMask, bool CPUAssumeITCMConflict) argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.cpp | 398 ScheduleDAGMILive *DAG = createGenericSchedLive(C); variable
412 ScheduleDAGMI *DAG variable
[all...] |