1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about Hexagon target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonTargetMachine.h"
14#include "Hexagon.h"
15#include "HexagonISelLowering.h"
16#include "HexagonLoopIdiomRecognition.h"
17#include "HexagonMachineScheduler.h"
18#include "HexagonTargetObjectFile.h"
19#include "HexagonTargetTransformInfo.h"
20#include "HexagonVectorLoopCarriedReuse.h"
21#include "TargetInfo/HexagonTargetInfo.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/CodeGen/TargetPassConfig.h"
24#include "llvm/IR/LegacyPassManager.h"
25#include "llvm/IR/Module.h"
26#include "llvm/Passes/PassBuilder.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/TargetRegistry.h"
29#include "llvm/Transforms/IPO/PassManagerBuilder.h"
30#include "llvm/Transforms/Scalar.h"
31
32using namespace llvm;
33
34static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
35  cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
36
37static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
38  cl::init(true), cl::desc("Enable RDF-based optimizations"));
39
40static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
41  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
42
43static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
44  cl::Hidden, cl::ZeroOrMore, cl::init(false),
45  cl::desc("Disable Hexagon Addressing Mode Optimization"));
46
47static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
48  cl::Hidden, cl::ZeroOrMore, cl::init(false),
49  cl::desc("Disable Hexagon CFG Optimization"));
50
51static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
52  cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
53
54static cl::opt<bool> DisableStoreWidening("disable-store-widen",
55  cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
56
57static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
58  cl::init(true), cl::Hidden, cl::ZeroOrMore,
59  cl::desc("Early expansion of MUX"));
60
61static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
62  cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
63
64static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
65  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
66
67static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
68  cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
69
70static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
71  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
72
73static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
74  cl::desc("Enable converting conditional transfers into MUX instructions"));
75
76static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
77  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
78  "predicate instructions"));
79
80static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
81  cl::init(false), cl::Hidden, cl::ZeroOrMore,
82  cl::desc("Enable loop data prefetch on Hexagon"));
83
84static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
85  cl::desc("Disable splitting double registers"));
86
87static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
88  cl::Hidden, cl::desc("Bit simplification"));
89
90static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
91  cl::Hidden, cl::desc("Loop rescheduling"));
92
93static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
94  cl::Hidden, cl::desc("Disable backend optimizations"));
95
96static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
97  cl::Hidden, cl::ZeroOrMore, cl::init(false),
98  cl::desc("Enable Hexagon Vector print instr pass"));
99
100static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
101  cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
102
103static cl::opt<bool> EnableVectorCombine("hexagon-vector-combine", cl::Hidden,
104  cl::ZeroOrMore, cl::init(true), cl::desc("Enable HVX vector combining"));
105
106static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
107  cl::Hidden, cl::ZeroOrMore, cl::init(true),
108  cl::desc("Simplify the CFG after atomic expansion pass"));
109
110static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
111                                        cl::ZeroOrMore, cl::init(true),
112                                        cl::desc("Enable instsimplify"));
113
114/// HexagonTargetMachineModule - Note that this is used on hosts that
115/// cannot link in a library unless there are references into the
116/// library.  In particular, it seems that it is not possible to get
117/// things to work on Win32 without this.  Though it is unused, do not
118/// remove it.
119extern "C" int HexagonTargetMachineModule;
120int HexagonTargetMachineModule = 0;
121
122static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
123  ScheduleDAGMILive *DAG =
124    new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
125  DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
126  DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
127  DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
128  DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
129  return DAG;
130}
131
132static MachineSchedRegistry
133SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
134                    createVLIWMachineSched);
135
136namespace llvm {
137  extern char &HexagonExpandCondsetsID;
138  void initializeHexagonBitSimplifyPass(PassRegistry&);
139  void initializeHexagonConstExtendersPass(PassRegistry&);
140  void initializeHexagonConstPropagationPass(PassRegistry&);
141  void initializeHexagonEarlyIfConversionPass(PassRegistry&);
142  void initializeHexagonExpandCondsetsPass(PassRegistry&);
143  void initializeHexagonGenMuxPass(PassRegistry&);
144  void initializeHexagonHardwareLoopsPass(PassRegistry&);
145  void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
146  void initializeHexagonNewValueJumpPass(PassRegistry&);
147  void initializeHexagonOptAddrModePass(PassRegistry&);
148  void initializeHexagonPacketizerPass(PassRegistry&);
149  void initializeHexagonRDFOptPass(PassRegistry&);
150  void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
151  void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
152  void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
153  void initializeHexagonVExtractPass(PassRegistry&);
154  Pass *createHexagonLoopIdiomPass();
155  Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
156
157  FunctionPass *createHexagonBitSimplify();
158  FunctionPass *createHexagonBranchRelaxation();
159  FunctionPass *createHexagonCallFrameInformation();
160  FunctionPass *createHexagonCFGOptimizer();
161  FunctionPass *createHexagonCommonGEP();
162  FunctionPass *createHexagonConstExtenders();
163  FunctionPass *createHexagonConstPropagationPass();
164  FunctionPass *createHexagonCopyToCombine();
165  FunctionPass *createHexagonEarlyIfConversion();
166  FunctionPass *createHexagonFixupHwLoops();
167  FunctionPass *createHexagonGenExtract();
168  FunctionPass *createHexagonGenInsert();
169  FunctionPass *createHexagonGenMux();
170  FunctionPass *createHexagonGenPredicate();
171  FunctionPass *createHexagonHardwareLoops();
172  FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
173                                     CodeGenOpt::Level OptLevel);
174  FunctionPass *createHexagonLoopRescheduling();
175  FunctionPass *createHexagonNewValueJump();
176  FunctionPass *createHexagonOptAddrMode();
177  FunctionPass *createHexagonOptimizeSZextends();
178  FunctionPass *createHexagonPacketizer(bool Minimal);
179  FunctionPass *createHexagonPeephole();
180  FunctionPass *createHexagonRDFOpt();
181  FunctionPass *createHexagonSplitConst32AndConst64();
182  FunctionPass *createHexagonSplitDoubleRegs();
183  FunctionPass *createHexagonStoreWidening();
184  FunctionPass *createHexagonVectorCombineLegacyPass();
185  FunctionPass *createHexagonVectorPrint();
186  FunctionPass *createHexagonVExtract();
187} // end namespace llvm;
188
189static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
190  return RM.getValueOr(Reloc::Static);
191}
192
193extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
194  // Register the target.
195  RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
196
197  PassRegistry &PR = *PassRegistry::getPassRegistry();
198  initializeHexagonBitSimplifyPass(PR);
199  initializeHexagonConstExtendersPass(PR);
200  initializeHexagonConstPropagationPass(PR);
201  initializeHexagonEarlyIfConversionPass(PR);
202  initializeHexagonGenMuxPass(PR);
203  initializeHexagonHardwareLoopsPass(PR);
204  initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
205  initializeHexagonNewValueJumpPass(PR);
206  initializeHexagonOptAddrModePass(PR);
207  initializeHexagonPacketizerPass(PR);
208  initializeHexagonRDFOptPass(PR);
209  initializeHexagonSplitDoubleRegsPass(PR);
210  initializeHexagonVectorCombineLegacyPass(PR);
211  initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
212  initializeHexagonVExtractPass(PR);
213}
214
215HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
216                                           StringRef CPU, StringRef FS,
217                                           const TargetOptions &Options,
218                                           Optional<Reloc::Model> RM,
219                                           Optional<CodeModel::Model> CM,
220                                           CodeGenOpt::Level OL, bool JIT)
221    // Specify the vector alignment explicitly. For v512x1, the calculated
222    // alignment would be 512*alignment(i1), which is 512 bytes, instead of
223    // the required minimum of 64 bytes.
224    : LLVMTargetMachine(
225          T,
226          "e-m:e-p:32:32:32-a:0-n16:32-"
227          "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
228          "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
229          TT, CPU, FS, Options, getEffectiveRelocModel(RM),
230          getEffectiveCodeModel(CM, CodeModel::Small),
231          (HexagonNoOpt ? CodeGenOpt::None : OL)),
232      TLOF(std::make_unique<HexagonTargetObjectFile>()) {
233  initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
234  initAsmInfo();
235}
236
237const HexagonSubtarget *
238HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
239  AttributeList FnAttrs = F.getAttributes();
240  Attribute CPUAttr =
241      FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
242  Attribute FSAttr =
243      FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
244
245  std::string CPU =
246      CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
247  std::string FS =
248      FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
249  // Append the preexisting target features last, so that +mattr overrides
250  // the "unsafe-fp-math" function attribute.
251  // Creating a separate target feature is not strictly necessary, it only
252  // exists to make "unsafe-fp-math" force creating a new subtarget.
253
254  if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
255    FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
256
257  auto &I = SubtargetMap[CPU + FS];
258  if (!I) {
259    // This needs to be done before we create a new subtarget since any
260    // creation will depend on the TM and the code generation flags on the
261    // function that reside in TargetOptions.
262    resetTargetOptions(F);
263    I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
264  }
265  return I.get();
266}
267
268void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
269  PMB.addExtension(
270    PassManagerBuilder::EP_LateLoopOptimizations,
271    [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
272      PM.add(createHexagonLoopIdiomPass());
273    });
274  PMB.addExtension(
275      PassManagerBuilder::EP_LoopOptimizerEnd,
276      [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
277        PM.add(createHexagonVectorLoopCarriedReuseLegacyPass());
278      });
279}
280
281void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
282  PB.registerLateLoopOptimizationsEPCallback(
283      [=](LoopPassManager &LPM, PassBuilder::OptimizationLevel Level) {
284        LPM.addPass(HexagonLoopIdiomRecognitionPass());
285      });
286  PB.registerLoopOptimizerEndEPCallback(
287      [=](LoopPassManager &LPM, PassBuilder::OptimizationLevel Level) {
288        LPM.addPass(HexagonVectorLoopCarriedReusePass());
289      });
290}
291
292TargetTransformInfo
293HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
294  return TargetTransformInfo(HexagonTTIImpl(this, F));
295}
296
297
298HexagonTargetMachine::~HexagonTargetMachine() {}
299
300namespace {
301/// Hexagon Code Generator Pass Configuration Options.
302class HexagonPassConfig : public TargetPassConfig {
303public:
304  HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
305    : TargetPassConfig(TM, PM) {}
306
307  HexagonTargetMachine &getHexagonTargetMachine() const {
308    return getTM<HexagonTargetMachine>();
309  }
310
311  ScheduleDAGInstrs *
312  createMachineScheduler(MachineSchedContext *C) const override {
313    return createVLIWMachineSched(C);
314  }
315
316  void addIRPasses() override;
317  bool addInstSelector() override;
318  void addPreRegAlloc() override;
319  void addPostRegAlloc() override;
320  void addPreSched2() override;
321  void addPreEmitPass() override;
322};
323} // namespace
324
325TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
326  return new HexagonPassConfig(*this, PM);
327}
328
329void HexagonPassConfig::addIRPasses() {
330  TargetPassConfig::addIRPasses();
331  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
332
333  if (!NoOpt) {
334    if (EnableInstSimplify)
335      addPass(createInstSimplifyLegacyPass());
336    addPass(createDeadCodeEliminationPass());
337  }
338
339  addPass(createAtomicExpandPass());
340
341  if (!NoOpt) {
342    if (EnableInitialCFGCleanup)
343      addPass(createCFGSimplificationPass(SimplifyCFGOptions()
344                                              .forwardSwitchCondToPhi(true)
345                                              .convertSwitchToLookupTable(true)
346                                              .needCanonicalLoops(false)
347                                              .hoistCommonInsts(true)
348                                              .sinkCommonInsts(true)));
349    if (EnableLoopPrefetch)
350      addPass(createLoopDataPrefetchPass());
351    if (EnableVectorCombine)
352      addPass(createHexagonVectorCombineLegacyPass());
353    if (EnableCommGEP)
354      addPass(createHexagonCommonGEP());
355    // Replace certain combinations of shifts and ands with extracts.
356    if (EnableGenExtract)
357      addPass(createHexagonGenExtract());
358  }
359}
360
361bool HexagonPassConfig::addInstSelector() {
362  HexagonTargetMachine &TM = getHexagonTargetMachine();
363  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
364
365  if (!NoOpt)
366    addPass(createHexagonOptimizeSZextends());
367
368  addPass(createHexagonISelDag(TM, getOptLevel()));
369
370  if (!NoOpt) {
371    if (EnableVExtractOpt)
372      addPass(createHexagonVExtract());
373    // Create logical operations on predicate registers.
374    if (EnableGenPred)
375      addPass(createHexagonGenPredicate());
376    // Rotate loops to expose bit-simplification opportunities.
377    if (EnableLoopResched)
378      addPass(createHexagonLoopRescheduling());
379    // Split double registers.
380    if (!DisableHSDR)
381      addPass(createHexagonSplitDoubleRegs());
382    // Bit simplification.
383    if (EnableBitSimplify)
384      addPass(createHexagonBitSimplify());
385    addPass(createHexagonPeephole());
386    // Constant propagation.
387    if (!DisableHCP) {
388      addPass(createHexagonConstPropagationPass());
389      addPass(&UnreachableMachineBlockElimID);
390    }
391    if (EnableGenInsert)
392      addPass(createHexagonGenInsert());
393    if (EnableEarlyIf)
394      addPass(createHexagonEarlyIfConversion());
395  }
396
397  return false;
398}
399
400void HexagonPassConfig::addPreRegAlloc() {
401  if (getOptLevel() != CodeGenOpt::None) {
402    if (EnableCExtOpt)
403      addPass(createHexagonConstExtenders());
404    if (EnableExpandCondsets)
405      insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
406    if (!DisableStoreWidening)
407      addPass(createHexagonStoreWidening());
408    if (!DisableHardwareLoops)
409      addPass(createHexagonHardwareLoops());
410  }
411  if (TM->getOptLevel() >= CodeGenOpt::Default)
412    addPass(&MachinePipelinerID);
413}
414
415void HexagonPassConfig::addPostRegAlloc() {
416  if (getOptLevel() != CodeGenOpt::None) {
417    if (EnableRDFOpt)
418      addPass(createHexagonRDFOpt());
419    if (!DisableHexagonCFGOpt)
420      addPass(createHexagonCFGOptimizer());
421    if (!DisableAModeOpt)
422      addPass(createHexagonOptAddrMode());
423  }
424}
425
426void HexagonPassConfig::addPreSched2() {
427  addPass(createHexagonCopyToCombine());
428  if (getOptLevel() != CodeGenOpt::None)
429    addPass(&IfConverterID);
430  addPass(createHexagonSplitConst32AndConst64());
431}
432
433void HexagonPassConfig::addPreEmitPass() {
434  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
435
436  if (!NoOpt)
437    addPass(createHexagonNewValueJump());
438
439  addPass(createHexagonBranchRelaxation());
440
441  if (!NoOpt) {
442    if (!DisableHardwareLoops)
443      addPass(createHexagonFixupHwLoops());
444    // Generate MUX from pairs of conditional transfers.
445    if (EnableGenMux)
446      addPass(createHexagonGenMux());
447  }
448
449  // Packetization is mandatory: it handles gather/scatter at all opt levels.
450  addPass(createHexagonPacketizer(NoOpt), false);
451
452  if (EnableVectorPrint)
453    addPass(createHexagonVectorPrint(), false);
454
455  // Add CFI instructions if necessary.
456  addPass(createHexagonCallFrameInformation(), false);
457}
458