| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 404 isWordAligned(SDValue Value, SelectionDAG &DAG) argument
1032 SelectionDAG &DAG = CLI.DAG; local
1060 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument
1106 LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1240 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1259 LowerCCCArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1591 SelectionDAG &DAG = DCI.DAG; local
1814 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 290 SelectionDAG &DAG; member in struct:llvm::SelectionDAG::DAGUpdateListener
317 DAGNodeDeletedListener(SelectionDAG &DAG, std::function<void(SDNode *, SDNode *)> Callback) argument
330 SelectionDAG &DAG; member in class:llvm::SelectionDAG::FlagInserter
[all...] |
| H A D | TargetInstrInfo.h | 1275 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, argument
[all...] |
| H A D | TargetLowering.h | 882 virtual bool shouldExpandShift(SelectionDAG &DAG, SDNod argument
541 isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const argument
564 isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const argument
2668 isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const argument
2714 isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const argument
3264 SelectionDAG &DAG; member in struct:llvm::TargetLoweringBase::TargetLowering::TargetLoweringOpt
3504 SelectionDAG &DAG; member in struct:llvm::TargetLoweringBase::TargetLowering::DAGCombinerInfo
3641 getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth = 0) const argument
3657 getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth = 0) const argument
3670 splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const argument
3679 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const argument
3726 SelectionDAG &DAG; member in struct:llvm::TargetLoweringBase::TargetLowering::CallLoweringInfo
3734 CallLoweringInfo(SelectionDAG &DAG) argument
4280 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const argument
4296 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const argument
4587 emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 604 SIScheduleBlockCreator(SIScheduleDAGMI *DAG) argument
1422 SIScheduleBlockScheduler(SIScheduleDAGMI *DAG, SISchedulerBlockSchedulerVariant Variant, SIScheduleBlocks BlocksStruct) argument
[all...] |
| H A D | AMDGPUISelDAGToDAG.cpp | 77 static SDNode *packConstantV2I16(const SDNode *N, SelectionDAG &DAG, argument
94 static SDNode *packNegConstantV2I16(const SDNode *N, SelectionDAG &DAG) { argument
918 getBaseWithOffsetUsingSplitOR(SelectionDAG &DAG, SDValue Addr, SDValue &N0, SDValue &N1) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 566 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
587 SelectionDAG &DAG = CLI.DAG; local
617 LowerCCCArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
803 LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
933 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1040 EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 74 void dump(const llvm::SelectionDAG *DAG) { argument
616 static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) { argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 171 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) argument
346 LowerCallResult( SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const argument
402 SelectionDAG &DAG = CLI.DAG; local
776 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1278 GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const argument
2329 getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy, SelectionDAG &DAG, MutableArrayRef<ConstantInt*> Consts) const argument
[all...] |
| H A D | HexagonISelDAGToDAG.cpp | 985 SelectionDAG &DAG = *CurDAG; local
1033 SelectionDAG &DAG = *CurDAG; local
1097 SelectionDAG &DAG = *CurDAG; local
1162 SelectionDAG &DAG = *CurDAG; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 345 SDValue M68kTargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, argument
210 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &DL) argument
358 EmitTailCallStoreRetAddr( SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetFI, EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &DL) const argument
377 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo &MFI, unsigned ArgIdx) const argument
446 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, const SDLoc &DL, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument
469 SelectionDAG &DAG = CLI.DAG; local
832 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
867 LowerFormalArguments( SDValue Chain, CallingConv::ID CCID, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1411 getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG) argument
1433 LowerAndToBT(SDValue And, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG) argument
1511 TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, bool IsFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) argument
1592 LowerTruncateToBT(SDValue Op, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG) argument
2007 isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) argument
3243 getSETCC(M68k::CondCode Cond, SDValue CCR, const SDLoc &dl, SelectionDAG &DAG) argument
3276 combineSetCCCCR(SDValue CCR, M68k::CondCode &CC, SelectionDAG &DAG, const M68kSubtarget &Subtarget) argument
3287 combineM68kSetCC(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget) argument
3299 combineM68kBrCond(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget) argument
3317 combineSUBX(SDNode *N, SelectionDAG &DAG) argument
3329 combineADDX(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI) argument
3343 SelectionDAG &DAG = DCI.DAG; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 392 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
534 SelectionDAG &DAG = CLI.DAG; local
1098 prepareTS1AM(SDValue Op, SelectionDAG &DAG, SDValue &Flag, SDValue &Bits) argument
1120 finalizeTS1AM(SDValue Op, SelectionDAG &DAG, SDValue Data, SDValue Bits) argument
1265 lowerLoadF128(SDValue Op, SelectionDAG &DAG) argument
1322 lowerStoreF128(SDValue Op, SelectionDAG &DAG) argument
1535 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget) argument
1556 lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget) argument
2548 SelectionDAG &DAG = DCI.DAG; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 482 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
597 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
717 shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
793 genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG) argument
829 performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget) argument
845 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
870 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
893 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
939 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
968 performSETCCCombine(SDNode *N, SelectionDAG &DAG) argument
981 performVSELECTCombine(SDNode *N, SelectionDAG &DAG) argument
998 performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
1027 SelectionDAG &DAG = DCI.DAG; local
1058 N->printrWithDepth(dbgs(), &DAG); dbgs() << "\\n=> \\n"; local
1059 Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\\n"); local
1287 initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG) argument
1295 extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) argument
1313 lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1361 lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1374 lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) argument
1418 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned = false) argument
1427 getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG) argument
1463 lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian) argument
1507 truncateVecElts(SDValue Op, SelectionDAG &DAG) argument
1520 lowerMSABitClear(SDValue Op, SelectionDAG &DAG) argument
1530 lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) argument
2293 lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget) argument
2367 lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget) argument
2553 lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2634 isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2666 lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2712 lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2759 lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2806 lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2854 lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2897 lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2933 lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
[all...] |
| H A D | MipsISelLowering.cpp | 148 getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
154 getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
160 getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
166 getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
172 getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
565 performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
642 createFPCmp(SelectionDAG &DAG, const SDValue &Op) argument
664 createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL) argument
674 performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
755 performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
782 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
864 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
1055 performSUBCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
1070 performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
1102 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
1155 SelectionDAG &DAG = DCI.DAG; local
2316 lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument
2363 lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument
2421 lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument
2458 lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument
2596 lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const argument
2647 createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset) argument
2729 createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset) argument
2746 lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle) argument
2775 lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat) argument
3141 SelectionDAG &DAG = CLI.DAG; local
3478 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, TargetLowering::CallLoweringInfo &CLI) const argument
3545 UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG) argument
3605 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4315 copyByValRegs( SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, MipsCCState &State) const argument
4368 passByValArg( SDValue Chain, const SDLoc &DL, std::deque<std::pair<unsigned, SDValue>> &RegsToPass, SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, const CCValAssign &VA) const argument
4464 writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, const SDLoc &DL, SelectionDAG &DAG, CCState &State) const argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 367 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
381 LowerFormalArguments_32( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
576 LowerFormalArguments_64( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
692 hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, const CallBase *Call) argument
717 SelectionDAG &DAG = CLI.DAG; local
1864 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
2153 LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const argument
2303 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2319 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2336 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2365 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2393 LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2414 LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2433 LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2470 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2506 LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2526 LowerVAARG(SDValue Op, SelectionDAG &DAG) argument
2550 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2615 getFLUSHW(SDValue Op, SelectionDAG &DAG) argument
2622 getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush = false) argument
2655 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2664 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) argument
2699 LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode) argument
2733 LowerF128Load(SDValue Op, SelectionDAG &DAG) argument
2774 LowerLOAD(SDValue Op, SelectionDAG &DAG) argument
2786 LowerF128Store(SDValue Op, SelectionDAG &DAG) argument
2822 LowerSTORE(SDValue Op, SelectionDAG &DAG) argument
2845 LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) argument
2888 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument
2939 LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2987 LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 802 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg) { argument
826 SelectionDAG &DAG = CLI.DAG; local
1112 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1540 getCppExceptionSymNode(SDValue Op, unsigned TagIndex, SelectionDAG &DAG) argument
1975 unrollVectorShift(SDValue Op, SelectionDAG &DAG) argument
2056 auto &DAG = DCI.DAG; local
2081 auto &DAG = DCI.DAG; local
2129 auto &DAG = DCI.DAG; local
2194 auto &DAG = DCI.DAG; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 1186 SDValue NVPTXTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, argument
1408 SelectionDAG &DAG = CLI.DAG; local
2409 getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const argument
2444 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4319 SelectionDAG &DAG = DCI.DAG; local
4752 ReplaceLoadVector(SDNode *N, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) argument
4881 ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGISel.cpp | 1024 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) argument
2791 MatchStateUpdater(SelectionDAG &DAG, SDNode **NodeToMatch, SmallVectorImpl<std::pair<SDValue, SDNode *>> &RN, SmallVectorImpl<MatchScope> &MS) argument
[all...] |
| H A D | LegalizeVectorTypes.cpp | 3197 CollectOpsToWiden(SelectionDAG &DAG, const TargetLowering &TLI, SmallVectorImpl<SDValue> &ConcatOps, unsigned ConcatEnd, EVT VT, EVT MaxVT, EVT WidenVT) argument
5140 FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, unsigned Width, EVT WidenVT, unsigned Align = 0, unsigned WidenEx = 0) argument
5212 BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, SmallVectorImpl<SDValue> &LdOps, unsigned Start, unsigned End) argument
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| H A D | LegalizeIntegerTypes.cpp | 885 SaturateWidenedDIVFIX(SDValue V, SDLoc &dl, unsigned SatW, bool Signed, const TargetLowering &TLI, SelectionDAG &DAG) argument
913 earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS, unsigned Scale, const TargetLowering &TLI, SelectionDAG &DAG, unsigned SatW = 0) argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1574 SelectionDAG &DAG; member in class:__anon2142::WidenVector
1577 WidenVector(SelectionDAG &DAG) : DAG(DAG) {} argument
1595 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) { argument
3311 static SDNode *extractSubReg(SelectionDAG *DAG, EV argument
3338 insertSubReg(SelectionDAG *DAG, EVT VT, SDValue V) argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineScheduler.cpp | 1593 clusterNeighboringMemOps( ArrayRef<MemOpInfo> MemOpRecords, bool FastCluster, ScheduleDAGInstrs *DAG) argument
1708 groupMemOps( ArrayRef<MemOpInfo> MemOps, ScheduleDAGInstrs *DAG, DenseMap<unsigned, SmallVector<MemOpInfo, 32>> &Groups) argument
1739 apply(ScheduleDAGInstrs *DAG) argument
1820 constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) argument
1945 ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs); local
2020 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) argument
2623 initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) argument
3486 ScheduleDAGMILive *DAG = local
3684 ScheduleDAGMILive *DAG = nullptr; member in class:__anon1826::ILPScheduler
3899 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G); local
3914 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G); local
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| H A D | MachinePipeliner.cpp | 1220 createAdjacencyStructure( SwingSchedulerDAG *DAG) argument
1366 apply(ScheduleDAGInstrs *DAG) argument
2465 multipleIterations(SUnit *SU, SwingSchedulerDAG *DAG) argument
2476 computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG) argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 6399 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, argument
|
| H A D | X86ISelDAGToDAG.cpp | 1818 insertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) argument
1836 foldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
1880 foldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, X86ISelAddressMode &AM) argument
1972 foldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
2059 foldMaskedShiftToBEXTR(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM, const X86Subtarget &Subtarget) argument
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