| /freebsd-10-stable/contrib/llvm/lib/MC/ |
| H A D | MCCodeGenInfo.cpp | 18 void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/CppBackend/ |
| H A D | CPPTargetMachine.h | 25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.cpp | 29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCTargetDesc.cpp | 69 createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430TargetMachine.cpp | 27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreTargetMachine.cpp | 23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetMachine.cpp | 67 HexagonTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCTargetDesc.cpp | 53 createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXMCTargetDesc.cpp | 54 createNVPTXMCCodeGenInfo( StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
| H A D | AMDGPUTargetMachine.cpp | 52 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcTargetMachine.cpp | 28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
85 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
97 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetMachine.cpp | 22 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/XCore/MCTargetDesc/ |
| H A D | XCoreMCTargetDesc.cpp | 65 createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | BoolAssignmentChecker.cpp | 81 ConstraintManager &CM = C.getConstraintManager(); local
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| H A D | NonNullParamChecker.cpp | 115 ConstraintManager &CM = C.getConstraintManager(); local
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| /freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
| H A D | LLVMTargetMachine.cpp | 76 LLVMTargetMachine(const Target &T, StringRef Triple, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 45 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
70 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
96 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsTargetMachine.cpp | 56 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
118 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
127 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 66 NVPTXTargetMachine( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
80 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
88 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetMachine.cpp | 73 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
94 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
104 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/R600/MCTargetDesc/ |
| H A D | AMDGPUMCTargetDesc.cpp | 57 createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCTargetDesc.cpp | 127 createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
| H A D | X86TargetMachine.cpp | 33 X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
57 X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
78 X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 72 createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 224 createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|