| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 1652 Instruction *InstCombiner::foldICmpAndShift(ICmpInst &Cmp, BinaryOperator *And, argument
1736 foldICmpAndConstConst(ICmpInst &Cmp, BinaryOperator *And, const APInt &C1) argument
1844 foldICmpAndConstant(ICmpInst &Cmp, BinaryOperator *And, const APInt &C) argument
1925 Value *And = Builder.CreateAnd(OrOp0, ~(*MaskC)); local
2127 Value *And = Builder.CreateAnd(X, Mask, Shl->getName() + ".mask"); local
2139 Value *And = Builder.CreateAnd(X, Mask, Shl->getName() + ".mask"); local
2149 Value *And = Builder.CreateAnd(X, (~C).lshr(ShiftAmt->getZExtValue())); local
2157 Value *And = local
2272 Value *And = Builder.CreateAnd(X, Mask, Shr->getName() + ".mask"); local
2303 Value *And = Builder.CreateAnd(SRem->getOperand(0), MaskC); local
3035 Value *And = Builder.CreateAnd(BOp0, NotBOC); local
4282 Value *And = Builder.CreateAnd(Xor, Builder.getInt(AndVal), local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 4974 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); local
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2112 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); local
2269 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); local
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 8194 SDValue And; local
8888 SDValue And local
11039 SDValue And = DAG.getNode(ISD::AND, DL, local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4683 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL); local
4736 SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Add, MaskC); local
4854 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask); local
5097 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode), local
5100 DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And); local
5113 SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(), local
5122 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0), local
5124 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And); local
5196 combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) argument
8346 SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask); local
9003 SDValue And = DAG.getNode(ISD::AND, DL, N0.getValueType(), N0, N1_0); local
9813 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift, local
10118 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, local
10367 SDValue And = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT); local
10441 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6133 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, local
13074 SDValue And local
15440 SDValue And = CmpZ->getOperand(0); local
[all...] |