| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCExpandPseudos.cpp | 62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, argument
114 unsigned AddrReg = MI.getOperand(0).getReg(); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 223 Register AddrReg = MI.getOperand(2).getReg(); local
285 Register AddrReg = MI.getOperand(2).getReg(); local
425 Register AddrReg = MI.getOperand(3).getReg(); local
537 Register AddrReg local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 116 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); variable
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| H A D | X86SpeculativeLoadHardening.cpp | 1162 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass); local
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| H A D | X86InstructionSelector.cpp | 1455 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass); local
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| H A D | X86FastISel.cpp | 3790 Register AddrReg = createResultReg(&X86::GR64RegClass); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 106 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); variable
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| H A D | ARMExpandPseudoInsts.cpp | 1554 Register AddrReg = MI.getOperand(2).getReg(); local
1673 Register AddrReg = MI.getOperand(2).getReg(); local
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| H A D | ARMFastISel.cpp | 1321 unsigned AddrReg = getRegForValue(I->getOperand(0)); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 505 unsigned SeqReg, AddrReg; local
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| H A D | AArch64ExpandPseudoInsts.cpp | 191 Register AddrReg = MI.getOperand(2).getReg(); local
271 Register AddrReg = MI.getOperand(3).getReg(); local
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| H A D | AArch64FastISel.cpp | 2228 unsigned AddrReg = getRegForValue(PtrV); local
2550 unsigned AddrReg = getRegForValue(BI->getOperand(0)); local
2087 emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg, MachineMemOperand *MMO) argument
5122 const unsigned AddrReg = constrainOperandRegClass( local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 65 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); variable
164 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); variable
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 269 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); local
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| H A D | MipsISelLowering.cpp | 2559 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 741 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 100 auto AddrReg = MIRBuilder.buildFrameIndex( variable
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| H A D | SILoadStoreOptimizer.cpp | 134 const MachineOperand *AddrReg[MaxAddressRegs]; member in struct:__anon3979::SILoadStoreOptimizer::CombineInfo
1007 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); local
1107 const MachineOperand *AddrReg = local
[all...] |
| H A D | SIInstrInfo.cpp | 350 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1857 unsigned AddrReg = getRegForValue(I->getOperand(0)); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3191 Register AddrReg = MI.getOperand(1).getReg(); local
|