video/stm32/stm32_dsi.c

71 /* dsi color format coding according to the datasheet */
99 static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
101 	writel(val, dsi->base + reg);
104 static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
106 	return readl(dsi->base + reg);
109 static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
111 	dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
114 static inline void dsi_clear(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
116 	dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
119 static inline void dsi_update_bits(struct stm32_dsi_priv *dsi, u32 reg,
122 	dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
153 static int dsi_pll_get_params(struct stm32_dsi_priv *dsi,
164 	fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
165 	fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
213 	struct stm32_dsi_priv *dsi = dev_get_priv(dev);
220 	dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
221 	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
229 	dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
230 	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
244 	struct stm32_dsi_priv *dsi = dev_get_priv(dev);
246 	dev_dbg(dev, "Set mode %p enable %ld\n", dsi,
249 	if (!dsi)
259 		dsi_set(dsi, DSI_WCR, WCR_DSIEN);
261 		dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
269 	struct stm32_dsi_priv *dsi = dev_get_priv(dev);
275 	dsi->lane_min_kbps = LANE_MIN_KBPS;
276 	dsi->lane_max_kbps = LANE_MAX_KBPS;
277 	if (dsi->hw_version == HWVER_131) {
278 		dsi->lane_min_kbps *= 2;
279 		dsi->lane_max_kbps *= 2;
282 	pll_in_khz = dsi->pllref_clk / 1000;
289 	if (pll_out_khz > dsi->lane_max_kbps) {
290 		pll_out_khz = dsi->lane_max_kbps;
293 	if (pll_out_khz < dsi->lane_min_kbps) {
294 		pll_out_khz = dsi->lane_min_kbps;
302 	ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
313 	dsi_update_bits(dsi, DSI_WRPCR,	WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
318 	dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
321 	dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
324 	dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
373 		dev_err(dev, "No video dsi host detected %d\n", ret);
380 		dev_err(dev, "failed to initialize mipi dsi host\n");
401 		dev_err(dev, "failed to enable mipi dsi host\n");
432 		dev_err(dev, "dsi dt register address error\n");
436 	ret =  device_get_supply_regulator(dev, "phy-dsi-supply",
439 		dev_err(dev, "Warning: cannot get phy dsi supply\n");
471 		dev_err(dev, "missing dsi hardware reset\n");
505 	{ .compatible = "st,stm32-dsi"},
510 	.name				= "stm32-display-dsi",