nand/raw/vf610_nfc.c

203 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
205 	return readl(nfc->regs + reg);
210 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
212 	writel(val, nfc->regs + reg);
257 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
277 	vf610_nfc_clear_status(nfc->regs);
332 		struct vf610_nfc *nfc = mtd_to_nfc(mtd);
333 		if (nfc->chip.options & NAND_BUSWIDTH_16)
359 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
360 	int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
362 	nfc->buf_offset = max(column, 0);
363 	nfc->alt_buf = ALT_BUF_DATA;
369 		nfc->buf_offset = 0;
377 		trfr_sz += nfc->write_sz;
379 		vf610_nfc_transfer_size(nfc->regs, trfr_sz);
380 		vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
385 		vf610_nfc_transfer_size(nfc->regs, 0);
386 		vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
392 		vf610_nfc_transfer_size(nfc->regs, trfr_sz);
393 		vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
401 		vf610_nfc_transfer_size(nfc->regs, trfr_sz);
403 		vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
409 		nfc->alt_buf = ALT_BUF_ONFI;
411 		vf610_nfc_transfer_size(nfc->regs, trfr_sz);
412 		vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
420 		vf610_nfc_transfer_size(nfc->regs, 0);
421 		vf610_nfc_send_commands(nfc->regs, command,
427 		nfc->alt_buf = ALT_BUF_ID;
428 		nfc->buf_offset = 0;
429 		vf610_nfc_transfer_size(nfc->regs, 0);
430 		vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
436 		nfc->alt_buf = ALT_BUF_STAT;
437 		vf610_nfc_transfer_size(nfc->regs, 0);
438 		vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE);
446 	nfc->write_sz = 0;
452 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
453 	uint c = nfc->buf_offset;
456 	if (nfc->alt_buf)
459 	vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
461 	nfc->buf_offset += len;
468 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
469 	uint c = nfc->buf_offset;
473 	vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
475 	nfc->write_sz += l;
476 	nfc->buf_offset += l;
482 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
484 	uint c = nfc->buf_offset;
486 	switch (nfc->alt_buf) {
496 		c = nfc->buf_offset ^ 0x3;
500 		tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
503 	nfc->buf_offset++;
559 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
564 	int flips_threshold = nfc->chip.ecc.strength / 2;
580 	flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
587 	memset(dat, 0xff, nfc->chip.ecc.size);
619 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
626 	nfc->write_sz = mtd->writesize + mtd->oobsize;
637 static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum)
639 	struct nand_chip *chip = &nfc->chip;
652 	nand_set_controller_data(chip, nfc);
697 		dev_err(nfc->dev, "Unsupported flash page size\n");
704 			dev_err(nfc->dev, "Unsupported flash with hwecc\n");
710 			dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size);
711 			dev_err(nfc->dev, "Step size needs to be page size\n");
764 		.compatible = "fsl,vf610-nfc",
772 	struct vf610_nfc *nfc = dev_get_priv(dev);
779 	nfc->regs = devm_ioremap(dev, res.start, resource_size(&res));
780 	nfc->dev = dev;
781 	return vf610_nfc_nand_init(nfc, 0);
785 	.name = "vf610-nfc-dt",
808 	struct vf610_nfc *nfc;
810 	nfc = calloc(1, sizeof(*nfc));
811 	if (!nfc) {
816 	nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE;
817 	err = vf610_nfc_nand_init(nfc, 0);