Lines Matching defs:nc
213 int (*remove)(struct atmel_nand_controller *nc);
214 void (*nand_init)(struct atmel_nand_controller *nc,
313 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
323 ret = regmap_read_poll_timeout(nc->base.smc,
325 atmel_nfc_op_done(&nc->op,
331 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
332 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
336 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
337 dev_err(nc->base.dev, "Access to an undefined area\n");
341 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
342 dev_err(nc->base.dev, "Access while busy\n");
346 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
347 dev_err(nc->base.dev, "Wrong access size\n");
424 struct atmel_hsmc_nand_controller *nc;
427 nc = to_hsmc_nand_controller(nand->controller);
429 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
438 struct atmel_hsmc_nand_controller *nc;
440 nc = to_hsmc_nand_controller(nand->controller);
445 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
453 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
461 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
465 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
467 u8 *addrs = nc->op.addrs;
472 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
474 for (i = 0; i < nc->op.ncmds; i++)
475 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
477 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
478 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
480 op |= ATMEL_NFC_CSID(nc->op.cs) |
481 ATMEL_NFC_ACYCLE(nc->op.naddrs);
483 if (nc->op.ncmds > 1)
489 if (nc->op.data != ATMEL_NFC_NO_DATA) {
491 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
493 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
498 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
501 regmap_write(nc->io, op, addr);
503 ret = atmel_nfc_wait(nc, poll, 0);
505 dev_err(nc->base.dev,
510 memset(&nc->op, 0, sizeof(nc->op));
520 struct atmel_hsmc_nand_controller *nc;
522 nc = to_hsmc_nand_controller(nand->controller);
525 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
528 nc->op.addrs[nc->op.naddrs++] = dat;
530 if (nc->op.ncmds > 1)
533 nc->op.cmds[nc->op.ncmds++] = dat;
537 nc->op.cs = nand->activecs->id;
538 atmel_nfc_exec_op(nc, true);
547 struct atmel_nand_controller *nc;
549 nc = to_nand_controller(nand->controller);
560 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
562 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
570 struct atmel_hsmc_nand_controller *nc;
573 nc = to_hsmc_nand_controller(nand->controller);
576 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
579 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
588 struct atmel_hsmc_nand_controller *nc;
591 nc = to_hsmc_nand_controller(nand->controller);
594 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
597 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
605 struct atmel_hsmc_nand_controller *nc;
607 nc = to_hsmc_nand_controller(nand->controller);
610 nc->op.addrs[nc->op.naddrs++] = column;
616 nc->op.addrs[nc->op.naddrs++] = column >> 8;
620 nc->op.addrs[nc->op.naddrs++] = page;
621 nc->op.addrs[nc->op.naddrs++] = page >> 8;
624 nc->op.addrs[nc->op.naddrs++] = page >> 16;
631 struct atmel_nand_controller *nc;
634 nc = to_nand_controller(nand->controller);
641 dev_err(nc->dev,
659 struct atmel_nand_controller *nc;
664 nc = to_nand_controller(nand->controller);
671 dev_err(nc->dev,
694 struct atmel_nand_controller *nc;
699 nc = to_nand_controller(nand->controller);
706 dev_err(nc->dev,
823 struct atmel_hsmc_nand_controller *nc;
826 nc = to_hsmc_nand_controller(nand->controller);
830 nc->op.cmds[0] = NAND_CMD_SEQIN;
831 nc->op.ncmds = 1;
833 nc->op.cs = nand->activecs->id;
834 nc->op.data = ATMEL_NFC_WRITE_DATA;
840 ret = atmel_nfc_exec_op(nc, true);
843 dev_err(nc->base.dev,
858 nc->op.cmds[0] = NAND_CMD_PAGEPROG;
859 nc->op.ncmds = 1;
860 nc->op.cs = nand->activecs->id;
861 ret = atmel_nfc_exec_op(nc, true);
863 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
897 struct atmel_hsmc_nand_controller *nc;
900 nc = to_hsmc_nand_controller(nand->controller);
914 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
917 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
920 nc->op.cs = nand->activecs->id;
921 nc->op.data = ATMEL_NFC_READ_DATA;
927 ret = atmel_nfc_exec_op(nc, true);
930 dev_err(nc->base.dev,
1006 struct atmel_nand_controller *nc;
1009 nc = to_nand_controller(nand->controller);
1011 if (!nc->pmecc) {
1012 dev_err(nc->dev, "HW ECC not supported\n");
1016 if (nc->caps->legacy_of_bindings) {
1019 if (!ofnode_read_u32(nc->dev->node_, "atmel,pmecc-cap", &val))
1022 if (!ofnode_read_u32(nc->dev->node_,
1051 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1073 struct atmel_nand_controller *nc;
1077 nc = to_nand_controller(nand->controller);
1100 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1133 struct atmel_nand_controller *nc;
1136 nc = to_nand_controller(nand->controller);
1151 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1363 struct atmel_nand_controller *nc;
1368 nc = to_nand_controller(nand->controller);
1380 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1390 struct atmel_hsmc_nand_controller *nc;
1395 nc = to_hsmc_nand_controller(nand->controller);
1410 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1421 struct atmel_nand_controller *nc;
1423 nc = to_nand_controller(nand->controller);
1429 return nc->caps->ops->setup_data_interface(nand, csline, conf);
1432 static void atmel_nand_init(struct atmel_nand_controller *nc,
1438 mtd->dev->parent = nc->dev;
1439 nand->controller = &nc->base;
1449 if (!nc->mck || !nc->caps->ops->setup_data_interface)
1456 if (nc->pmecc)
1460 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1466 atmel_nand_init(nc, nand);
1485 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1490 atmel_nand_init(nc, nand);
1504 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1520 dev_err(nc->dev, "Missing or invalid reg property\n");
1524 nand = devm_kzalloc(nc->dev,
1529 dev_err(nc->dev, "Failed to allocate NAND object\n");
1541 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1551 dev_err(nc->dev, "Unable to read resource\n");
1570 dev_err(nc->dev, "Failed to get R/B gpio (err = %d)\n", ret);
1612 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1622 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1626 nc->caps->ops->nand_init(nc, nand);
1630 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1636 dev_err(nc->dev, "nand register failed: %d\n", ret);
1640 list_add_tail(&nand->node, &nc->chips);
1646 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1651 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1660 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1671 np = nc->dev->node_;
1675 dev_err(nc->dev, "missing #address-cells property\n");
1683 dev_err(nc->dev, "missing #size-cells property\n");
1692 nand = atmel_nand_create(nc, nand_np, reg_cells);
1698 ret = atmel_nand_controller_add_nand(nc, nand);
1706 atmel_nand_controller_remove_nands(nc);
1783 struct atmel_nand_controller *nc = to_nand_controller(nand->controller);
1787 ret = nc->caps->ops->ecc_init(chip);
1791 if (nc->caps->legacy_of_bindings || !ofnode_valid(nc->dev->node_)) {
1809 sprintf(mtd->name, "%s:nand.%d", nc->dev->name, nand->cs[0].id);
1820 atmel_nand_controller_init(struct atmel_nand_controller *nc,
1827 nc->base.ops = &atmel_nand_controller_ops;
1828 INIT_LIST_HEAD(&nc->chips);
1829 nc->dev = dev;
1830 nc->caps = caps;
1832 nc->pmecc = devm_atmel_pmecc_get(dev);
1833 if (IS_ERR(nc->pmecc)) {
1834 ret = PTR_ERR(nc->pmecc);
1842 if (nc->caps->legacy_of_bindings)
1845 nc->mck = devm_kzalloc(dev, sizeof(nc->mck), GFP_KERNEL);
1846 if (!nc->mck)
1849 clk_get_by_index(dev->parent, 0, nc->mck);
1850 if (IS_ERR(nc->mck)) {
1852 return PTR_ERR(nc->mck);
1862 nc->smc = syscon_node_to_regmap(args.node);
1863 if (IS_ERR(nc->smc)) {
1864 ret = PTR_ERR(nc->smc);
1873 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
1875 struct udevice *dev = nc->base.dev;
1884 if (nc->base.caps->legacy_of_bindings)
1888 nc->base.caps->ebi_csa_regmap_name,
1908 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
1910 nc->ebi_csa_regmap = syscon_node_to_regmap(args.node);
1911 if (IS_ERR(nc->ebi_csa_regmap)) {
1912 ret = PTR_ERR(nc->ebi_csa_regmap);
1925 static int atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
1927 struct udevice *dev = nc->base.dev;
1940 nc->hsmc_layout = atmel_hsmc_get_reg_layout(args.node);
1941 if (IS_ERR(nc->hsmc_layout)) {
1964 nc->io = syscon_node_to_regmap(args.node);
1965 if (IS_ERR(nc->io)) {
1966 ret = PTR_ERR(nc->io);
1983 nc->sram.virt = (void *)addr;
1989 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
1994 ret = atmel_nand_controller_remove_nands(nc);
1998 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2010 struct atmel_hsmc_nand_controller *nc;
2013 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2014 if (!nc)
2017 ret = atmel_nand_controller_init(&nc->base, dev, caps);
2021 ret = atmel_hsmc_nand_controller_init(nc);
2026 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2029 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2032 ret = atmel_nand_controller_add_nands(&nc->base);
2039 atmel_hsmc_nand_controller_remove(&nc->base);
2063 struct atmel_smc_nand_controller *nc;
2066 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2067 if (!nc)
2070 ret = atmel_nand_controller_init(&nc->base, dev, caps);
2074 ret = atmel_smc_nand_controller_init(nc);
2078 return atmel_nand_controller_add_nands(&nc->base);
2082 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2086 ret = atmel_nand_controller_remove_nands(nc);
2223 struct atmel_nand_controller *nc;
2225 nc = (struct atmel_nand_controller *)dev_get_driver_data(dev);
2227 return nc->caps->ops->remove(nc);