Lines Matching refs:Def
306 val raise'exception_def = Def
316 val rec'Index_def = Def
322 val reg'Index_def = Def
328 val write'rec'Index_def = Def
332 val write'reg'Index_def = Def
336 val rec'Random_def = Def
341 val reg'Random_def = Def
347 val write'rec'Random_def = Def
351 val write'reg'Random_def = Def
355 val rec'Wired_def = Def
360 val reg'Wired_def = Def
366 val write'rec'Wired_def = Def
370 val write'reg'Wired_def = Def
374 val rec'EntryLo_def = Def
381 val reg'EntryLo_def = Def
390 val write'rec'EntryLo_def = Def
394 val write'reg'EntryLo_def = Def
398 val rec'PageMask_def = Def
405 val reg'PageMask_def = Def
413 val write'rec'PageMask_def = Def
417 val write'reg'PageMask_def = Def
421 val rec'EntryHi_def = Def
429 val reg'EntryHi_def = Def
439 val write'rec'EntryHi_def = Def
443 val write'reg'EntryHi_def = Def
447 val rec'StatusRegister_def = Def
462 val reg'StatusRegister_def = Def
480 val write'rec'StatusRegister_def = Def
484 val write'reg'StatusRegister_def = Def
488 val rec'ConfigRegister_def = Def
498 val reg'ConfigRegister_def = Def
511 val write'rec'ConfigRegister_def = Def
515 val write'reg'ConfigRegister_def = Def
519 val rec'ConfigRegister1_def = Def
532 val reg'ConfigRegister1_def = Def
547 val write'rec'ConfigRegister1_def = Def
551 val write'reg'ConfigRegister1_def = Def
556 val rec'ConfigRegister2_def = Def
565 val reg'ConfigRegister2_def = Def
575 val write'rec'ConfigRegister2_def = Def
579 val write'reg'ConfigRegister2_def = Def
584 val rec'ConfigRegister3_def = Def
596 val reg'ConfigRegister3_def = Def
615 val write'rec'ConfigRegister3_def = Def
619 val write'reg'ConfigRegister3_def = Def
624 val rec'ConfigRegister6_def = Def
631 val reg'ConfigRegister6_def = Def
642 val write'rec'ConfigRegister6_def = Def
646 val write'reg'ConfigRegister6_def = Def
651 val rec'CauseRegister_def = Def
660 val reg'CauseRegister_def = Def
673 val write'rec'CauseRegister_def = Def
677 val write'reg'CauseRegister_def = Def
681 val rec'Context_def = Def
687 val reg'Context_def = Def
696 val write'rec'Context_def = Def
700 val write'reg'Context_def = Def
704 val rec'XContext_def = Def
711 val reg'XContext_def = Def
720 val write'rec'XContext_def = Def
724 val write'reg'XContext_def = Def
728 val rec'HWREna_def = Def
737 val reg'HWREna_def = Def
750 val write'rec'HWREna_def = Def
754 val write'reg'HWREna_def = Def
758 val ConditionalBranch_def = Def
773 val ConditionalBranchLikely_def = Def
796 val NotWordValue_def = Def
802 val ExceptionCode_def = Def
833 val SignalException_def = Def
949 val SignalCP1UnusableException_def = Def
965 val UserMode_def = Def
986 val SupervisorMode_def = Def
1007 val KernelMode_def = Def
1027 val GPR_def = Def
1034 val write'GPR_def = Def
1046 val HI_def = Def
1056 val write'HI_def = Def
1061 val LO_def = Def
1071 val write'LO_def = Def
1076 val CPR_def = Def
1124 val write'CPR_def = Def
1225 val BigEndianMem_def = Def
1231 val ReverseEndian_def = Def
1242 val BigEndianCPU_def = Def
1248 val AddressTranslation_def = Def
1252 val Aligned_def = Def
1257 val AdjustEndian_def = Def
1290 val ReadData_def = Def
1341 val LoadMemory_def = Def
1396 val loadByte_def = Def
1432 val loadHalf_def = Def
1468 val loadWord_def = Def
1505 val loadDoubleword_def = Def
1525 val Fetch_def = Def
1547 val WriteData_def = Def
1770 val StoreMemory_def = Def
1867 val storeWord_def = Def
1892 val storeDoubleword_def = Def
1907 val rec'FCSR_def = Def
1924 val reg'FCSR_def = Def
1947 val write'rec'FCSR_def = Def
1951 val write'reg'FCSR_def = Def
1955 val rec'FIR_def = Def
1964 val reg'FIR_def = Def
1976 val write'rec'FIR_def = Def
1980 val write'reg'FIR_def = Def
1984 val IntToWordMIPS_def = Def
1990 val IntToDWordMIPS_def = Def
1996 val PostOpF32_def = Def
2003 val PostOpF64_def = Def
2010 val FP32_Abs1985_def = Def
2015 val FP32_Neg1985_def = Def
2020 val FP64_Abs1985_def = Def
2025 val FP64_Neg1985_def = Def
2030 val FP64_Unordered_def = Def
2034 val FP32_Unordered_def = Def
2038 val Rounding_Mode_def = Def
2046 val dfn'ABS_D_def = Def
2084 val dfn'ABS_S_def = Def
2126 val dfn'ADD_D_def = Def
2157 val dfn'ADD_S_def = Def
2193 val dfn'BC1F_def = Def
2215 val dfn'BC1FL_def = Def
2237 val dfn'BC1T_def = Def
2257 val dfn'BC1TL_def = Def
2277 val dfn'C_cond_D_def = Def
2407 val dfn'C_cond_S_def = Def
2557 val dfn'CEIL_L_D_def = Def
2583 val dfn'CEIL_L_S_def = Def
2609 val dfn'CEIL_W_D_def = Def
2635 val dfn'CEIL_W_S_def = Def
2661 val dfn'CVT_D_L_def = Def
2687 val dfn'CVT_D_S_def = Def
2709 val dfn'CVT_D_W_def = Def
2749 val dfn'CVT_L_D_def = Def
2777 val dfn'CVT_L_S_def = Def
2805 val dfn'CVT_S_D_def = Def
2831 val dfn'CVT_S_L_def = Def
2859 val dfn'CVT_S_W_def = Def
2902 val dfn'CVT_W_D_def = Def
2930 val dfn'CVT_W_S_def = Def
2958 val dfn'DIV_D_def = Def
2989 val dfn'DIV_S_def = Def
3025 val dfn'FLOOR_L_D_def = Def
3051 val dfn'FLOOR_L_S_def = Def
3077 val dfn'FLOOR_W_D_def = Def
3103 val dfn'FLOOR_W_S_def = Def
3129 val dfn'LDC1_def = Def
3159 val dfn'LDXC1_def = Def
3192 val dfn'LWC1_def = Def
3237 val dfn'LWXC1_def = Def
3285 val dfn'MADD_D_def = Def
3334 val dfn'MADD_S_def = Def
3390 val dfn'MOV_D_def = Def
3411 val dfn'MOV_S_def = Def
3433 val dfn'MOVF_def = Def
3457 val dfn'MOVF_D_def = Def
3483 val dfn'MOVF_S_def = Def
3511 val dfn'MOVN_D_def = Def
3538 val dfn'MOVN_S_def = Def
3567 val dfn'MOVT_def = Def
3590 val dfn'MOVT_D_def = Def
3615 val dfn'MOVT_S_def = Def
3642 val dfn'MOVZ_D_def = Def
3667 val dfn'MOVZ_S_def = Def
3694 val dfn'MSUB_D_def = Def
3743 val dfn'MSUB_S_def = Def
3799 val dfn'MUL_D_def = Def
3830 val dfn'MUL_S_def = Def
3866 val dfn'NEG_D_def = Def
3904 val dfn'NEG_S_def = Def
3946 val dfn'ROUND_L_D_def = Def
3972 val dfn'ROUND_L_S_def = Def
3998 val dfn'ROUND_W_D_def = Def
4024 val dfn'ROUND_W_S_def = Def
4050 val dfn'SDC1_def = Def
4076 val dfn'SDXC1_def = Def
4105 val dfn'SQRT_D_def = Def
4133 val dfn'SQRT_S_def = Def
4164 val dfn'SUB_D_def = Def
4195 val dfn'SUB_S_def = Def
4231 val dfn'SWC1_def = Def
4268 val dfn'SWXC1_def = Def
4308 val dfn'TRUNC_L_D_def = Def
4334 val dfn'TRUNC_L_S_def = Def
4360 val dfn'TRUNC_W_D_def = Def
4386 val dfn'TRUNC_W_S_def = Def
4412 val dfn'DMFC1_def = Def
4431 val dfn'DMTC1_def = Def
4451 val dfn'MFC1_def = Def
4472 val dfn'MTC1_def = Def
4494 val dfn'CFC1_def = Def
4539 val dfn'CTC1_def = Def
4592 val dfn'UnknownFPInstruction_def = Def
4606 val dfn'ADDI_def = Def
4643 val dfn'ADDIU_def = Def
4672 val dfn'DADDI_def = Def
4695 val dfn'DADDIU_def = Def
4708 val dfn'SLTI_def = Def
4722 val dfn'SLTIU_def = Def
4736 val dfn'ANDI_def = Def
4749 val dfn'ORI_def = Def
4762 val dfn'XORI_def = Def
4775 val dfn'LUI_def = Def
4785 val dfn'ADD_def = Def
4830 val dfn'ADDU_def = Def
4867 val dfn'SUB_def = Def
4912 val dfn'SUBU_def = Def
4949 val dfn'DADD_def = Def
4974 val dfn'DADDU_def = Def
4988 val dfn'DSUB_def = Def
5013 val dfn'DSUBU_def = Def
5027 val dfn'SLT_def = Def
5043 val dfn'SLTU_def = Def
5059 val dfn'AND_def = Def
5073 val dfn'OR_def = Def
5087 val dfn'XOR_def = Def
5101 val dfn'NOR_def = Def
5117 val dfn'MOVN_def = Def
5132 val dfn'MOVZ_def = Def
5145 val dfn'MADD_def = Def
5201 val dfn'MADDU_def = Def
5257 val dfn'MSUB_def = Def
5313 val dfn'MSUBU_def = Def
5369 val dfn'MUL_def = Def
5413 val dfn'MULT_def = Def
5456 val dfn'MULTU_def = Def
5499 val dfn'DMULT_def = Def
5520 val dfn'DMULTU_def = Def
5541 val dfn'DIV_def = Def
5577 val dfn'DIVU_def = Def
5613 val dfn'DDIV_def = Def
5634 val dfn'DDIVU_def = Def
5655 val dfn'MFHI_def = Def
5666 val dfn'MFLO_def = Def
5677 val dfn'MTHI_def = Def
5687 val dfn'MTLO_def = Def
5697 val dfn'SLL_def = Def
5712 val dfn'SRL_def = Def
5741 val dfn'SRA_def = Def
5770 val dfn'SLLV_def = Def
5788 val dfn'SRLV_def = Def
5820 val dfn'SRAV_def = Def
5852 val dfn'DSLL_def = Def
5865 val dfn'DSRL_def = Def
5878 val dfn'DSRA_def = Def
5891 val dfn'DSLLV_def = Def
5907 val dfn'DSRLV_def = Def
5923 val dfn'DSRAV_def = Def
5939 val dfn'DSLL32_def = Def
5952 val dfn'DSRL32_def = Def
5965 val dfn'DSRA32_def = Def
5978 val dfn'TGE_def = Def
5990 val dfn'TGEU_def = Def
6002 val dfn'TLT_def = Def
6014 val dfn'TLTU_def = Def
6026 val dfn'TEQ_def = Def
6037 val dfn'TNE_def = Def
6051 val dfn'TGEI_def = Def
6063 val dfn'TGEIU_def = Def
6075 val dfn'TLTI_def = Def
6087 val dfn'TLTIU_def = Def
6099 val dfn'TEQI_def = Def
6110 val dfn'TNEI_def = Def
6123 val dfn'LB_def = Def
6133 val dfn'LBU_def = Def
6143 val dfn'LH_def = Def
6153 val dfn'LHU_def = Def
6163 val dfn'LW_def = Def
6173 val dfn'LWU_def = Def
6183 val dfn'LL_def = Def
6193 val dfn'LD_def = Def
6203 val dfn'LLD_def = Def
6213 val dfn'LWL_def = Def
6291 val dfn'LWR_def = Def
6376 val dfn'LDL_def = Def
6454 val dfn'LDR_def = Def
6541 val dfn'SB_def = Def
6569 val dfn'SH_def = Def
6598 val dfn'SW_def = Def
6609 val dfn'SD_def = Def
6620 val dfn'SC_def = Def
6637 val dfn'SCD_def = Def
6654 val dfn'SWL_def = Def
6712 val dfn'SWR_def = Def
6802 val dfn'SDL_def = Def
6876 val dfn'SDR_def = Def
6962 val dfn'SYNC_def = Def ("dfn'SYNC",Var("stype",FTy 5),LU)
6964 val dfn'BREAK_def = Def
6970 val dfn'SYSCALL_def = Def
6976 val dfn'ERET_def = Def
7047 val dfn'MTC0_def = Def
7069 val dfn'DMTC0_def = Def
7091 val dfn'MFC0_def = Def
7117 val dfn'DMFC0_def = Def
7141 val dfn'J_def = Def
7153 val dfn'JAL_def = Def
7171 val dfn'JR_def = Def
7183 val dfn'JALR_def = Def
7199 val dfn'BEQ_def = Def
7212 val dfn'BNE_def = Def
7227 val dfn'BLEZ_def = Def
7239 val dfn'BGTZ_def = Def
7251 val dfn'BLTZ_def = Def
7263 val dfn'BGEZ_def = Def
7275 val dfn'BLTZAL_def = Def
7292 val dfn'BGEZAL_def = Def
7309 val dfn'BEQL_def = Def
7322 val dfn'BNEL_def = Def
7337 val dfn'BLEZL_def = Def
7349 val dfn'BGTZL_def = Def
7361 val dfn'BLTZL_def = Def
7373 val dfn'BGEZL_def = Def
7385 val dfn'BLTZALL_def = Def
7402 val dfn'BGEZALL_def = Def
7421 val dfn'TLBP_def = Def
7427 val dfn'TLBR_def = Def
7433 val dfn'TLBWI_def = Def
7439 val dfn'TLBWR_def = Def
7445 val dfn'CACHE_def = Def
7454 val dfn'RDHWR_def = Def
7463 val dfn'ReservedInstruction_def = Def
7469 val dfn'Unpredictable_def = Def
7479 val Run_def = Def
8656 val COP1Decode_def = Def
9839 val LDC1Decode_def = Def
9847 val LWC1Decode_def = Def
9855 val SDC1Decode_def = Def
9863 val SWC1Decode_def = Def
9871 val MOVCIDecode_def = Def
9895 val COP3Decode_def = Def
10046 val Decode_def = Def
13919 val Next_def = Def
14001 val COP1Encode_def = Def
14256 val form1_def = Def
14263 val form2_def = Def
14267 val form3_def = Def
14274 val form4_def = Def
14279 val form5_def = Def
14286 val form6_def = Def
14291 val Encode_def = Def