Minor changes within floating-point theory.

• The operations float_negate1985 and float_abs1985 have been removed.
• Added a predicate float_is_signalling and renamed float_some_nan to float_some_qnan.
• Fixed problem with EQ_tm and GT_tm being swapped in binary_ieeeSyntax.

Generalise some MIPS floating-point instructions.

The BC1* and C.cond.fmt instructions are no longer specialised to $fcc0 only.

Update MIPS tools to support floating-point operations.

This currently omits support for the floating-point memory operations, such as LDC1 and SDC1. (They should be straightforward to support.)

Fix for MIPS encoder.

Add MIPS floating-point instruction encoder.

Update MIPS model to include Mike Roe’s floating-point specification.

Also improve treatment of memory operations (so as to be more similar to the CHERI model).

Update the ARMv7, ARM-M0, MIPS and x86-64 models.

Exported from the latest version of L3.

Update for the latest version of L3.

Changes have been made when exporting operations of the form:

`f : args -> state -> value * state`

If the state is not changed then this is now exported as

`f : args -> state -> value`

If the state is changed but the `value` type is `unit` then it this is now exported as

`f : args -> state -> state`.

Various updates to the L3 examples.

Most changes are brought about by improvements and generalisations within stateLib and utilsLib.

A Holmakefile has been added to a new decompilers sub-directory and some *decomp_demoScript files have also been added. This makes it easier to perform regression testing.

Update for the latest version of L3, which has additional floating-point support.

Cover IEEE754:1985 behaviour for "abs" and "neg". Also adds support for "compare", "toInt" and "fromInt" at the machine level.

Update model for latest version of L3.

Update MIPS model and tools.

The model now includes an instruction encoder.

Update the MIPS example.

The model should detect more instances of branches in the branch delay slot, which is categorised as being unpredictable.

Update the MIPS model to catch more unpredictable cases.

Fix for MIPS SUBU instruction.

Update for L3 examples.

Fixes a potential problem with the handling of word replicate.

Moves some shared code into stateLib (the register_combinations function).

Some other minor fixes.

Update MIPS model and associated tools.

Update for MIPS model and tools.

Simplifies handling of load/stores. (The tools now no longer attempt to accommodate reverse endian mode.)

Fixes modelling of exceptions occurring for an instruction in the branch delay slot. (This has to be properly processed and flagged using the component CP0.Cause.BD.)

Also fixed errors in the specifications of the MADD, MADDU, MSUB, MSUBU, SWR and SDR instructions. (Thanks to Mike Roe for testing the model.)

Update to MIPS model.

(Just structural changes.)

Support for ERET MIPS instruction.

Fix for MIPS jumps instructions.

Update MIPS model.

Now includes the instructions: MOVN, MOVZ, MUL, MADD, MADDU, MSUB and MSUBU. This extends the model beyond vanilla MIPS III.

Update ISA models.

The new models are generated by the latest version of L3. This mostly results in just a few formatting (pretty-printing) changes. However, bit-patterns are now expanded out in a different manner. Specifically, applications of “word_extract” (over the match word) are replaced with applications of “v2w” (over the bits generated by “boolify”). Some minor updates were needed to accommodate this change.

Minor change to ISA models.

All ‘rst record fields are now prefixed by the type name.

Update to the MIPS model.

The decoder is now more strict.

Extend support for MTC0 and MFC0 instructions (MIPS).

Some minor formatting (printing) changes in the L3 instruction set models.

Add MIPS model (and tools) to examples.