io/igb/igb_mac.c

191 	s32 ret_val;
199 	ret_val = e1000_read_pcie_cap_reg(hw,
201 	if (ret_val)
330 	s32 ret_val = E1000_SUCCESS;
336 	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
338 	if (ret_val) {
356 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
357 		if (ret_val) {
380 	return (ret_val);
635 	s32 ret_val;
647 		ret_val = E1000_SUCCESS;
656 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
657 	if (ret_val)
676 		ret_val = -E1000_ERR_CONFIG;
693 	ret_val = e1000_config_fc_after_link_up_generic(hw);
694 	if (ret_val)
698 	return (ret_val);
715 	s32 ret_val = E1000_SUCCESS;
749 		ret_val = e1000_config_fc_after_link_up_generic(hw);
750 		if (ret_val) {
769 	return (ret_val);
786 	s32 ret_val = E1000_SUCCESS;
818 		ret_val = e1000_config_fc_after_link_up_generic(hw);
819 		if (ret_val) {
882 	return (ret_val);
898 	s32 ret_val = E1000_SUCCESS;
915 		ret_val = e1000_set_default_fc_generic(hw);
916 		if (ret_val)
930 	ret_val = hw->mac.ops.setup_physical_interface(hw);
931 	if (ret_val)
947 	ret_val = e1000_set_fc_watermarks_generic(hw);
950 	return (ret_val);
964 	s32 ret_val = E1000_SUCCESS;
975 	ret_val = e1000_commit_fc_settings_generic(hw);
976 	if (ret_val)
999 		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1005 	return (ret_val);
1044 	s32 ret_val = E1000_SUCCESS;
1070 		ret_val = hw->mac.ops.check_for_link(hw);
1071 		if (ret_val) {
1082 	return (ret_val);
1097 	s32 ret_val = E1000_SUCCESS;
1150 		ret_val = -E1000_ERR_CONFIG;
1158 	return (ret_val);
1172 	s32 ret_val = E1000_SUCCESS;
1199 	return (ret_val);
1212 	s32 ret_val = E1000_SUCCESS;
1226 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1228 	if (ret_val) {
1242 	return (ret_val);
1259 	s32 ret_val = E1000_SUCCESS;
1302 		ret_val = -E1000_ERR_CONFIG;
1309 	return (ret_val);
1326 	s32 ret_val = E1000_SUCCESS;
1340 			ret_val = e1000_force_mac_fc_generic(hw);
1343 			ret_val = e1000_force_mac_fc_generic(hw);
1346 	if (ret_val) {
1363 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1364 		if (ret_val)
1366 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1367 		if (ret_val)
1383 		ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1385 		if (ret_val)
1387 		ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1389 		if (ret_val)
1487 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1488 		if (ret_val) {
1500 		ret_val = e1000_force_mac_fc_generic(hw);
1501 		if (ret_val) {
1508 	return (ret_val);
1583 	s32 ret_val = E1000_SUCCESS;
1601 		ret_val = -E1000_ERR_NVM;
1621 		ret_val = -E1000_ERR_NVM;
1626 	return (ret_val);
1659 	s32 ret_val = E1000_SUCCESS;
1672 		ret_val = -E1000_ERR_RESET;
1677 	return (ret_val);
1691 	s32 ret_val;
1695 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1696 	if (ret_val) {
1705 	return (ret_val);
1717 	s32 ret_val;
1726 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1727 	if (ret_val)
1773 	return (ret_val);
1787 	s32 ret_val = E1000_SUCCESS;
1792 		ret_val = -E1000_ERR_CONFIG;
1811 	return (ret_val);
1824 	s32 ret_val = E1000_SUCCESS;
1829 		ret_val = -E1000_ERR_CONFIG;
1836 	return (ret_val);
1976 	s32 ret_val = E1000_SUCCESS;
1997 		ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2002 	return (ret_val);
2085 	s32 ret_val = E1000_SUCCESS;
2092 		ret_val = -E1000_ERR_CONFIG;
2097 	return (ret_val);
2116 	s32 ret_val = E1000_SUCCESS;
2133 		ret_val = -E1000_ERR_PHY;
2138 	return (ret_val);