drv/audiots/audiots.c

469 	ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten,
653 	ddi_put32(handle, &regs->aud_regs.ap_stop, TS_ALL_DMA_ENGINES);
654 	ddi_put32(handle, &regs->aud_regs.ap_ainten, TS_ALL_DMA_OFF);
657 	ddi_put32(handle, &regs->aud_regs.ap_volume, 0x0);
660 	ddi_put32(handle, &regs->aud_regs.ap_cir_gc, AP_CIR_GC_ENDLP_IE);
697 	OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_global_control,
702 	OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl,
705 	AND_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl,
751 		data = &state->ts_regs->aud_regs.ap_acrd_35D_data;
753 		data = &state->ts_regs->aud_regs.ap_acrdwr_data;
927 	uint32_t		*gcptr = &state->ts_regs->aud_regs.ap_cir_gc;
1026 	uint32_t		*stimer = &state->ts_regs->aud_regs.ap_stimer;
1033 		addr = &state->ts_regs->aud_regs.ap_acrd_35D_reg;
1034 		data = &state->ts_regs->aud_regs.ap_acrd_35D_data;
1036 		addr = &state->ts_regs->aud_regs.ap_acrdwr_reg;
1037 		data = &state->ts_regs->aud_regs.ap_acrdwr_data;
1150 	uint16_t	*data_addr = &state->ts_regs->aud_regs.ap_acrdwr_data;
1151 	uint16_t	*reg_addr = &state->ts_regs->aud_regs.ap_acrdwr_reg;
1269 	ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop,
1337 	ddi_put32(handle, &regs->aud_regs.ap_stop, port->tp_dma_mask);
1340 	ddi_put32(handle, &regs->aud_regs.ap_start, port->tp_dma_mask);
1511 	ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten,
1514 	ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop,
1517 	ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_aint,