arm/vm/assembler_arm_32.hpp

69   AsmOperand(Register rm, AsmShift shift, Register rs) {
70     assert(rm != PC && rs != PC, "unpredictable instruction");
71     _encoding = rs->encoding() << 8 | shift << 5 | 1 << 4 | rm->encoding();
284   void mnemonic(Register rdlo, Register rdhi, Register rm, Register rs,                  \
287               rdlo->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding()); \
289   void mnemonic##s(Register rdlo, Register rdhi, Register rm, Register rs,               \
292               rdlo->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding()); \
301   void mul(Register rd, Register rm, Register rs, AsmCondition cond = al) {
303               rs->encoding() << 8 | 0x9 << 4 | rm->encoding());
306   void muls(Register rd, Register rm, Register rs, AsmCondition cond = al) {
308               rs->encoding() << 8 | 0x9 << 4 | rm->encoding());
311   void mla(Register rd, Register rm, Register rs, Register rn, AsmCondition cond = al) {
313               rn->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding());
316   void mlas(Register rd, Register rm, Register rs, Register rn, AsmCondition cond = al) {
318               rn->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding());
386   void strex(Register rs, Register rd, Address addr, AsmCondition cond = al) {
387     assert(rd != PC && rs != PC &&
388            rs != rd && rs != addr.base(), "unpredictable instruction");
390               rs->encoding()  << 12 | 0xf90 | rd->encoding());
399   void strexd(Register rs, Register rd, Address addr, AsmCondition cond = al) {
400     assert(rd != PC && rs != PC &&
401            rs != rd && rs != addr.base(), "unpredictable instruction");
403               rs->encoding()  << 12 | 0xf90 | rd->encoding());