amd/amdgpu/uvd_v7_0.c

89 	if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
123 	if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
161 	if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
409 		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
415 			r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
446 			ring = &adev->uvd.inst[j].ring;
450 					     &adev->uvd.inst[j].irq, 0,
457 			ring = &adev->uvd.inst[j].ring_enc[i];
472 					     &adev->uvd.inst[j].irq, 0,
509 			amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
538 		ring = &adev->uvd.inst[j].ring;
579 			ring = &adev->uvd.inst[j].ring_enc[i];
692 				lower_32_bits(adev->uvd.inst[i].gpu_addr));
694 				upper_32_bits(adev->uvd.inst[i].gpu_addr));
703 				lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
705 				upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
710 				lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
712 				upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
758 		WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
759 		*adev->uvd.inst[i].ring_enc[0].wptr_cpu_addr = 0;
760 		adev->uvd.inst[i].ring_enc[0].wptr = 0;
761 		adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
816 			ring = &adev->uvd.inst[i].ring;
834 							    lower_32_bits(adev->uvd.inst[i].gpu_addr));
836 							    upper_32_bits(adev->uvd.inst[i].gpu_addr));
846 						    lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
848 						    upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
853 						    lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
855 						    upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
919 			ring = &adev->uvd.inst[i].ring_enc[0];
975 		ring = &adev->uvd.inst[k].ring;
1113 		ring = &adev->uvd.inst[k].ring_enc[0];
1120 		ring = &adev->uvd.inst[k].ring_enc[1];
1498 		adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1501 		adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1510 	if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1522 	if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1524 	srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1552 	if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1592 		amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
1595 		amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
1599 			amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
1872 		adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
1873 		adev->uvd.inst[i].ring.me = i;
1886 			adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1887 			adev->uvd.inst[j].ring_enc[i].me = j;
1906 		adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
1907 		adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;