dev/pci/com_pci.c

63 #define HREAD4(sc, reg)							\
64 	(bus_space_read_4((sc)->sc.sc_iot, (sc)->sc.sc_ioh, (reg)))
65 #define HWRITE4(sc, reg, val)						\
66 	bus_space_write_4((sc)->sc.sc_iot, (sc)->sc.sc_ioh, (reg), (val))
67 #define HSET4(sc, reg, bits)						\
68 	HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
69 #define HCLR4(sc, reg, bits)						\
70 	HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
79 	struct com_softc	 sc;
110 	struct com_pci_softc *sc = (struct com_pci_softc *)self;
117 	sc->sc_pc = pa->pa_pc;
118 	sc->sc_id = pa->pa_id;
119 	sc->sc.sc_frequency = COM_FREQ;
120 	sc->sc.sc_uarttype = COM_UART_16550;
121 	sc->sc.sc_reg_width = 4;
122 	sc->sc.sc_reg_shift = 2;
127 	    &sc->sc.sc_iot, &sc->sc.sc_ioh, &sc->sc.sc_iobase, &sc->sc_ios, 0)) {
137 		caps = HREAD4(sc, LPSS_CAPS);
139 			bus_space_unmap(sc->sc.sc_iot, sc->sc.sc_ioh,
140 			    sc->sc_ios);
145 		HWRITE4(sc, LPSS_RESETS, 0);
146 		HWRITE4(sc, LPSS_RESETS, LPSS_RESETS_FUNC | LPSS_RESETS_IDMA);
147 		HWRITE4(sc, LPSS_REMAP_ADDR, sc->sc.sc_iobase);
151 		m = n = HREAD4(sc, LPSS_CLK);
158 		sc->sc.sc_frequency = freq;
162 		bus_space_unmap(sc->sc.sc_iot, sc->sc.sc_ioh, sc->sc_ios);
168 	sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY,
169 	    com_pci_intr_designware, &sc->sc, sc->sc.sc_dev.dv_xname);
170 	if (sc->sc_ih == NULL) {
171 		bus_space_unmap(sc->sc.sc_iot, sc->sc.sc_ioh, sc->sc_ios);
179 	com_attach_subr(&sc->sc);
185 	struct com_pci_softc *sc = (struct com_pci_softc *)self;
191 	if (sc->sc_ih != NULL) {
192 		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
193 		sc->sc_ih = NULL;
195 	if (sc->sc_ios != 0) {
196 		bus_space_unmap(sc->sc.sc_iot, sc->sc.sc_ioh, sc->sc_ios);
197 		sc->sc_ios = 0;
206 	struct com_pci_softc *sc = (struct com_pci_softc *)self;
209 	if (PCI_VENDOR(sc->sc_id) != PCI_VENDOR_INTEL)
215 			HWRITE4(sc, i * sizeof(uint32_t), sc->sc_priv[i]);
221 			sc->sc_priv[i] = HREAD4(sc, i * sizeof(uint32_t));
234 	struct com_softc *sc = cookie;
236 	com_read_reg(sc, com_usr);
238 	return comintr(sc);