| #
1.4 |
|
24-May-2024 |
jsg |
remove unneeded includes; ok miod@
|
|
Revision tags: OPENBSD_7_4_BASE OPENBSD_7_5_BASE
|
|
| #
1.3 |
|
11-Sep-2023 |
mvs |
Remove unnecessary <sys/selinfo.h> includes.
ok jsg
|
|
Revision tags: OPENBSD_7_2_BASE OPENBSD_7_3_BASE
|
|
| #
1.2 |
|
06-Apr-2022 |
naddy |
constify struct cfattach
|
|
Revision tags: OPENBSD_6_7_BASE OPENBSD_6_8_BASE OPENBSD_6_9_BASE OPENBSD_7_0_BASE OPENBSD_7_1_BASE
|
|
| #
1.1 |
|
06-Mar-2020 |
patrick |
Add a PCI attachment driver for com(4). Intel has been removing legacy
I/O-Ports on recent machines. Instead the UARTs are memory mapped PCI-
devices, as part of a so-called Low Power Subsystem (LPSS).
Such an LPSS is also used for I2C and SPI, though they use different PCI
device ids. Each LPSS contains the actual device, and some registers to
control clocks, resets, etc. These private registers need to be saved
and restored upon suspend/resume. Also we should read the current clock
settings to calculate the frequency supplied to the device.
The UART controller itself is based on Synopsys DesignWare IP, like
we're used to from various ARM-based machines
ok kettenis@
|
| #
1.3 |
|
11-Sep-2023 |
mvs |
Remove unnecessary <sys/selinfo.h> includes.
ok jsg
|
|
Revision tags: OPENBSD_7_2_BASE OPENBSD_7_3_BASE
|
|
| #
1.2 |
|
06-Apr-2022 |
naddy |
constify struct cfattach
|
|
Revision tags: OPENBSD_6_7_BASE OPENBSD_6_8_BASE OPENBSD_6_9_BASE OPENBSD_7_0_BASE OPENBSD_7_1_BASE
|
|
| #
1.1 |
|
06-Mar-2020 |
patrick |
Add a PCI attachment driver for com(4). Intel has been removing legacy
I/O-Ports on recent machines. Instead the UARTs are memory mapped PCI-
devices, as part of a so-called Low Power Subsystem (LPSS).
Such an LPSS is also used for I2C and SPI, though they use different PCI
device ids. Each LPSS contains the actual device, and some registers to
control clocks, resets, etc. These private registers need to be saved
and restored upon suspend/resume. Also we should read the current clock
settings to calculate the frequency supplied to the device.
The UART controller itself is based on Synopsys DesignWare IP, like
we're used to from various ARM-based machines
ok kettenis@
|
| #
1.2 |
|
06-Apr-2022 |
naddy |
constify struct cfattach
|
|
Revision tags: OPENBSD_6_7_BASE OPENBSD_6_8_BASE OPENBSD_6_9_BASE OPENBSD_7_0_BASE OPENBSD_7_1_BASE
|
|
| #
1.1 |
|
06-Mar-2020 |
patrick |
Add a PCI attachment driver for com(4). Intel has been removing legacy
I/O-Ports on recent machines. Instead the UARTs are memory mapped PCI-
devices, as part of a so-called Low Power Subsystem (LPSS).
Such an LPSS is also used for I2C and SPI, though they use different PCI
device ids. Each LPSS contains the actual device, and some registers to
control clocks, resets, etc. These private registers need to be saved
and restored upon suspend/resume. Also we should read the current clock
settings to calculate the frequency supplied to the device.
The UART controller itself is based on Synopsys DesignWare IP, like
we're used to from various ARM-based machines
ok kettenis@
|
| #
1.1 |
|
06-Mar-2020 |
patrick |
Add a PCI attachment driver for com(4). Intel has been removing legacy
I/O-Ports on recent machines. Instead the UARTs are memory mapped PCI-
devices, as part of a so-called Low Power Subsystem (LPSS).
Such an LPSS is also used for I2C and SPI, though they use different PCI
device ids. Each LPSS contains the actual device, and some registers to
control clocks, resets, etc. These private registers need to be saved
and restored upon suspend/resume. Also we should read the current clock
settings to calculate the frequency supplied to the device.
The UART controller itself is based on Synopsys DesignWare IP, like
we're used to from various ARM-based machines
ok kettenis@
|