Target/PowerPC/PPCISelLowering.cpp

11943   MVT PVT = getPointerTy(MF->getDataLayout());
11944   assert((PVT == MVT::i64 || PVT == MVT::i32) &&
11987   const int64_t LabelOffset = 1 * PVT.getStoreSize();
11988   const int64_t TOCOffset   = 3 * PVT.getStoreSize();
11989   const int64_t BPOffset    = 4 * PVT.getStoreSize();
11992   const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
12075   MVT PVT = getPointerTy(MF->getDataLayout());
12076   assert((PVT == MVT::i64 || PVT == MVT::i32) &&
12080     (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
12083   unsigned FP  = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
12084   unsigned SP  = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
12086       (PVT == MVT::i64)
12093   const int64_t LabelOffset = 1 * PVT.getStoreSize();
12094   const int64_t SPOffset    = 2 * PVT.getStoreSize();
12095   const int64_t TOCOffset   = 3 * PVT.getStoreSize();
12096   const int64_t BPOffset    = 4 * PVT.getStoreSize();
12103   if (PVT == MVT::i64) {
12115   if (PVT == MVT::i64) {
12127   if (PVT == MVT::i64) {
12139   if (PVT == MVT::i64) {
12151   if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
12161           TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
12162   BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));