Lines Matching refs:ready
279 #define USTAT_TXRDY 0x02 /* UART tx ready */
280 #define USTAT_RXRDY 0x01 /* UART rx ready */
446 unsigned ready:1;
521 /* wait for ready */
656 to wait for it to become ready */
825 && s->dma_dac1.ready) {
847 && s->dma_dac2.ready) {
872 && s->dma_adc.ready) {
905 db->mapped = db->ready = 0;
917 db->ready = db->mapped = 0;
957 db->ready = 1;
1272 if (s->dma_dac1.mapped || !s->dma_dac1.ready)
1307 if (s->dma_dac2.mapped || !s->dma_dac2.ready)
1353 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1430 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1507 if (!s->dma_dac2.ready && prog_dmabuf_dac2(s))
1512 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1630 s->dma_adc.ready = 0;
1635 s->dma_dac2.ready = 0;
1646 s->dma_adc.ready = 0;
1657 s->dma_dac2.ready = 0;
1674 s->dma_adc.ready = 0;
1685 s->dma_dac2.ready = 0;
1706 s->dma_adc.ready = 0;
1717 s->dma_dac2.ready = 0;
1746 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1757 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1771 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1788 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1809 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1822 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1842 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
2043 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2109 if (!s->dma_dac1.ready && prog_dmabuf_dac1(s))
2190 s->dma_dac1.ready = 0;
2199 s->dma_dac1.ready = 0;
2214 s->dma_dac1.ready = 0;
2233 s->dma_dac1.ready = 0;
2254 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2265 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2284 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2295 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)