Lines Matching refs:ioc3
30 #define IOC3_NAME "ioc3-eth"
64 #include <asm/sn/ioc3.h>
78 struct ioc3 *regs;
169 * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
172 #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
173 #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
174 #define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
175 #define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
176 #define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
177 #define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
178 #define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
179 #define ioc3_r_eier() be32_to_cpu(ioc3->eier)
180 #define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
181 #define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
182 #define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
183 #define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
184 #define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
185 #define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
186 #define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
187 #define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
188 #define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
189 #define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
190 #define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
191 #define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
192 #define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
193 #define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
194 #define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
195 #define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
196 #define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
197 #define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
198 #define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
199 #define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
200 #define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
201 #define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
202 #define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
203 #define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
204 #define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
205 #define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
206 #define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
207 #define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
208 #define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
209 #define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
210 #define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
211 #define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
212 #define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
213 #define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
214 #define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
215 #define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
216 #define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
217 #define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
218 #define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
219 #define ioc3_r_micr() be32_to_cpu(ioc3->micr)
220 #define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
221 #define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
222 #define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
223 #define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
224 #define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
231 static int nic_wait(struct ioc3 *ioc3)
242 static int nic_reset(struct ioc3 *ioc3)
247 presence = nic_wait(ioc3);
250 nic_wait(ioc3);
255 static inline int nic_read_bit(struct ioc3 *ioc3)
260 result = nic_wait(ioc3);
262 nic_wait(ioc3);
267 static inline void nic_write_bit(struct ioc3 *ioc3, int bit)
274 nic_wait(ioc3);
280 static u32 nic_read_byte(struct ioc3 *ioc3)
286 result = (result >> 1) | (nic_read_bit(ioc3) << 7);
294 static void nic_write_byte(struct ioc3 *ioc3, int byte)
302 nic_write_bit(ioc3, bit);
306 static u64 nic_find(struct ioc3 *ioc3, int *last)
311 nic_reset(ioc3);
313 nic_write_byte(ioc3, 0xf0);
317 a = nic_read_bit(ioc3);
318 b = nic_read_bit(ioc3);
334 nic_write_bit(ioc3, address & (1UL << index));
341 nic_write_bit(ioc3, a);
351 static int nic_init(struct ioc3 *ioc3)
362 reg = nic_find(ioc3, &save);
376 nic_reset(ioc3);
379 nic_write_byte(ioc3, 0x55);
381 nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
409 struct ioc3 *ioc3 = ip->regs;
417 if (!nic_init(ioc3))
428 nic_write_byte(ioc3, 0xf0);
429 nic_write_byte(ioc3, 0x00);
430 nic_write_byte(ioc3, 0x00);
433 nic[i] = nic_read_byte(ioc3);
463 struct ioc3 *ioc3 = ip->regs;
491 struct ioc3 *ioc3 = ip->regs;
503 struct ioc3 *ioc3 = ip->regs;
516 struct ioc3 *ioc3 = ip->regs;
593 struct ioc3 *ioc3 = ip->regs;
670 struct ioc3 *ioc3 = ip->regs;
749 struct ioc3 *ioc3 = ip->regs;
773 struct ioc3 *ioc3 = ip->regs;
960 struct ioc3 *ioc3 = ip->regs;
990 struct ioc3 *ioc3 = ip->regs;
991 volatile u32 *ssram0 = &ioc3->ssram[0x0000];
992 volatile u32 *ssram1 = &ioc3->ssram[0x4000];
1013 struct ioc3 *ioc3 = ip->regs;
1050 struct ioc3 *ioc3 = ip->regs;
1125 * addresses on a partitioned machine. Since we currently use the ioc3
1127 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1130 * port 0. So, we just use one serial port from each ioc3 (since the
1140 * around ioc3 oddities in this respect.
1145 static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
1175 port.membase = (unsigned char *) &ioc3->sregs.uarta;
1178 port.membase = (unsigned char *) &ioc3->sregs.uartb;
1188 struct ioc3 *ioc3;
1225 err = pci_request_regions(pdev, "ioc3");
1238 ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
1239 if (!ioc3) {
1245 ip->regs = ioc3;
1248 ioc3_serial_probe(pdev, ioc3);
1268 printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1332 struct ioc3 *ioc3 = ip->regs;
1337 iounmap(ioc3);
1353 .name = "ioc3-eth",
1373 struct ioc3 *ioc3 = ip->regs;
1629 struct ioc3 *ioc3 = ip->regs;