Lines Matching refs:r10
216 lis r10,EBIU0_BRCR0_VAL@h
217 ori r10,r10,EBIU0_BRCR0_VAL@l
218 mtdcr ebiu0_brcr0,r10
219 lis r10,EBIU0_BRCRH0_VAL@h
220 ori r10,r10,EBIU0_BRCRH0_VAL@l
221 mtdcr ebiu0_brcrh0,r10
226 lis r10,EBIU0_BRCR1_VAL@h
227 ori r10,r10,EBIU0_BRCR1_VAL@l
228 mtdcr ebiu0_brcr1,r10
229 lis r10,EBIU0_BRCRH1_VAL@h
230 ori r10,r10,EBIU0_BRCRH1_VAL@l
231 mtdcr ebiu0_brcrh1,r10
236 lis r10,EBIU0_BRCR2_VAL@h
237 ori r10,r10,EBIU0_BRCR2_VAL@l
238 mtdcr ebiu0_brcr2,r10
239 lis r10,EBIU0_BRCRH2_VAL@h
240 ori r10,r10,EBIU0_BRCRH2_VAL@l
241 mtdcr ebiu0_brcrh2,r10
246 lis r10,EBIU0_BRCR3_VAL@h
247 ori r10,r10,EBIU0_BRCR3_VAL@l
248 mtdcr ebiu0_brcr3,r10
249 lis r10,EBIU0_BRCRH3_VAL@h
250 ori r10,r10,EBIU0_BRCRH3_VAL@l
251 mtdcr ebiu0_brcrh3,r10
256 lis r10,EBIU0_BRCR4_VAL@h
257 ori r10,r10,EBIU0_BRCR4_VAL@l
258 mtdcr ebiu0_brcr4,r10
259 lis r10,EBIU0_BRCRH4_VAL@h
260 ori r10,r10,EBIU0_BRCRH4_VAL@l
261 mtdcr ebiu0_brcrh4,r10
266 lis r10,EBIU0_BRCR5_VAL@h
267 ori r10,r10,EBIU0_BRCR5_VAL@l
268 mtdcr ebiu0_brcr5,r10
269 lis r10,EBIU0_BRCRH5_VAL@h
270 ori r10,r10,EBIU0_BRCRH5_VAL@l
271 mtdcr ebiu0_brcrh5,r10
276 lis r10,EBIU0_BRCR6_VAL@h
277 ori r10,r10,EBIU0_BRCR6_VAL@l
278 mtdcr ebiu0_brcr6,r10
279 lis r10,EBIU0_BRCRH6_VAL@h
280 ori r10,r10,EBIU0_BRCRH6_VAL@l
281 mtdcr ebiu0_brcrh6,r10
286 lis r10,EBIU0_BRCR7_VAL@h
287 ori r10,r10,EBIU0_BRCR7_VAL@l
288 mtdcr ebiu0_brcr7,r10
289 lis r10,EBIU0_BRCRH7_VAL@h
290 ori r10,r10,EBIU0_BRCRH7_VAL@l
291 mtdcr ebiu0_brcrh7,r10
315 lis r10,CBS0_CR_VAL@h /* r10 <- CBS Cntl Reg val */
316 ori r10,r10,CBS0_CR_VAL@l
317 mtdcr cbs0_cr,r10
322 lis r10,CIC0_CR_VAL@h /* r10 <- CIC Cntl Reg val */
323 ori r10,r10,CIC0_CR_VAL@l
324 mtdcr cic0_cr,r10
326 lis r10,CIC0_SEL3_VAL@h /* r10 <- CIC SEL3 Reg val */
327 ori r10,r10,CIC0_SEL3_VAL@l
328 mtdcr cic0_sel3,r10
330 lis r10,CIC0_VCR_VAL@h /* r10 <- CIC Vid C-Reg val */
331 ori r10,r10,CIC0_VCR_VAL@l
332 mtdcr cic0_vcr,r10
337 li r10,0x0000
338 mtspr sgr,r10
339 mtspr dcwr,r10
344 li r10,0x0000 /* r10 <- 0 */
345 mtdcr ebiu0_besr,r10 /* clr Bus Err Syndrome Reg */
346 mtspr esr,r10 /* clr Exceptn Syndrome Reg */
347 mttcr r10 /* timer control register */
349 mtdcr uic0_er,r10 /* disable all interrupts */
352 lis r10, 0x00600e00@h
353 ori r10,r10,0x00600e00@l
354 mtdcr uic0_pr,r10
356 li r10,0x00000020 /* UIC_EIR1 */
357 mtdcr uic0_tr,r10
359 lis r10,0xFFFF /* r10 <- 0xFFFFFFFF */
360 ori r10,r10,0xFFFF /* */
361 mtdbsr r10 /* clear/reset the dbsr */
362 mtdcr uic0_sr,r10 /* clear pending interrupts */
364 li r10,0x1000 /* set Machine Exception bit*/
365 oris r10,r10,0x2 /* set Criticl Exception bit*/
366 mtmsr r10 /* change MSR */
371 li r10,0x0000
372 mtxer r10
377 lis r10, STB_GPIO0_TC@h /* Three-state control */
378 ori r10,r10,STB_GPIO0_TC@l
381 stw r11,0(r10)
383 lis r10, STB_GPIO0_OS_0_31@h /* output select 0-31 */
384 ori r10,r10,STB_GPIO0_OS_0_31@l
387 stw r11,0(r10)
389 lis r10, STB_GPIO0_OS_32_63@h /* output select 32-63 */
390 ori r10,r10,STB_GPIO0_OS_32_63@l
393 stw r11,0(r10)
395 lis r10, STB_GPIO0_TS_0_31@h /* three-state select 0-31 */
396 ori r10,r10,STB_GPIO0_TS_0_31@l
399 stw r11,0(r10)
401 lis r10, STB_GPIO0_TS_32_63@h /* three-state select 32-63 */
402 ori r10,r10,STB_GPIO0_TS_32_63@l
405 stw r11,0(r10)
407 lis r10, STB_GPIO0_OD@h /* open drain */
408 ori r10,r10,STB_GPIO0_OD@l
411 stw r11,0(r10)
413 lis r10, STB_GPIO0_IS_1_0_31@h /* input select 1, 0-31 */
414 ori r10,r10,STB_GPIO0_IS_1_0_31@l
417 stw r11,0(r10)
419 lis r10, STB_GPIO0_IS_1_32_63@h /* input select 1, 32-63 */
420 ori r10,r10,STB_GPIO0_IS_1_32_63@l
423 stw r11,0(r10)
425 lis r10, STB_GPIO0_IS_2_0_31@h /* input select 2, 0-31 */
426 ori r10,r10,STB_GPIO0_IS_2_0_31@l
429 stw r11,0(r10)
431 lis r10, STB_GPIO0_IS_2_32_63@h /* input select 2, 32-63 */
432 ori r10,r10,STB_GPIO0_IS_2_32_63@l
435 stw r11,0(r10)
437 lis r10, STB_GPIO0_IS_3_0_31@h /* input select 3, 0-31 */
438 ori r10,r10,STB_GPIO0_IS_3_0_31@l
441 stw r11,0(r10)
443 lis r10, STB_GPIO0_IS_3_32_63@h /* input select 3, 32-63 */
444 ori r10,r10,STB_GPIO0_IS_3_32_63@l
447 stw r11,0(r10)
449 lis r10, STB_GPIO0_SS_1@h /* sync select 1 */
450 ori r10,r10,STB_GPIO0_SS_1@l
453 stw r11,0(r10)
455 lis r10, STB_GPIO0_SS_2@h /* sync select 2 */
456 ori r10,r10,STB_GPIO0_SS_2@l
459 stw r11,0(r10)
461 lis r10, STB_GPIO0_SS_3@h /* sync select 3 */
462 ori r10,r10,STB_GPIO0_SS_3@l
465 stw r11,0(r10)
470 lis r10, STB_XILINX1_REG0@h /* init Xilinx1 Reg 0 */
471 ori r10,r10,STB_XILINX1_REG0@l
473 sth r11,0(r10)
475 lis r10, STB_XILINX1_REG1@h /* init Xilinx1 Reg 1 */
476 ori r10,r10,STB_XILINX1_REG1@l
478 sth r11,0(r10)
480 lis r10, STB_XILINX1_REG2@h /* init Xilinx1 Reg 2 */
481 ori r10,r10,STB_XILINX1_REG2@l
483 sth r11,0(r10)
485 lis r10, STB_XILINX1_REG3@h /* init Xilinx1 Reg 3 */
486 ori r10,r10,STB_XILINX1_REG3@l
488 sth r11,0(r10)
490 lis r10, STB_XILINX1_REG4@h /* init Xilinx1 Reg 4 */
491 ori r10,r10,STB_XILINX1_REG4@l
493 sth r11,0(r10)
495 lis r10, STB_XILINX1_REG5@h /* init Xilinx1 Reg 5 */
496 ori r10,r10,STB_XILINX1_REG5@l
498 sth r11,0(r10)
500 lis r10, STB_XILINX1_REG6@h /* init Xilinx1 Reg 6 */
501 ori r10,r10,STB_XILINX1_REG6@l
503 sth r11,0(r10)
505 lis r10, STB_XILINX1_FLUSH@h /* latch registers in Xilinx*/
506 ori r10,r10,STB_XILINX1_FLUSH@l
508 sth r11,0(r10)
513 lis r10, STB_XILINX2_REG0@h /* init Xilinx2 Reg 0 */
514 ori r10,r10,STB_XILINX2_REG0@l
516 sth r11,0(r10)
518 lis r10, STB_XILINX2_REG1@h /* init Xilinx2 Reg 1 */
519 ori r10,r10,STB_XILINX2_REG1@l
521 sth r11,0(r10)
523 lis r10, STB_XILINX2_REG2@h /* init Xilinx2 Reg 2 */
524 ori r10,r10,STB_XILINX2_REG2@l
526 sth r11,0(r10)
548 lis r10,0x6C00
549 ori r10,r10,0x0000
550 mtdcr hsmc0_gr,r10
555 lis r10,0x0037
556 ori r10,r10,0x0000
557 mtdcr hsmc0_data,r10
562 lis r10,HSMC0_BR0_VAL@h
563 ori r10,r10,HSMC0_BR0_VAL@l
564 mtdcr hsmc0_br0,r10
569 lis r10,HSMC0_BR1_VAL@h
570 ori r10,r10,HSMC0_BR1_VAL@l
571 mtdcr hsmc0_br1,r10
576 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */
577 ori r10,r10,0x0000
578 mtdcr hsmc0_cr0,r10
584 lis r10,0x8078 /* AUTO-REFRESH */
585 ori r10,r10,0x0000
586 mtdcr hsmc0_cr0,r10
592 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */
593 ori r10,r10,0x8000
594 mtdcr hsmc0_cr0,r10
603 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */
604 ori r10,r10,0x0000
605 mtdcr hsmc0_cr1,r10
611 lis r10,0x8078 /* AUTO-REFRESH */
612 ori r10,r10,0x0000
613 mtdcr hsmc0_cr1,r10
619 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */
620 ori r10,r10,0x8000
621 mtdcr hsmc0_cr1,r10
630 lis r10,0x0FE1
631 ori r10,r10,0x0000
632 mtdcr hsmc0_crr,r10
657 lis r10,0x6C00
658 ori r10,r10,0x0000
659 mtdcr hsmc1_gr,r10
664 lis r10,0x0037
665 ori r10,r10,0x0000
666 mtdcr hsmc1_data,r10
671 lis r10,HSMC1_BR0_VAL@h
672 ori r10,r10,HSMC1_BR0_VAL@l
673 mtdcr hsmc1_br0,r10
678 lis r10,HSMC1_BR1_VAL@h
679 ori r10,r10,HSMC1_BR1_VAL@l
680 mtdcr hsmc1_br1,r10
685 lis r10,0x8077 /* PRECHARGE ALL DEVICE BANKS */
686 ori r10,r10,0x0000
687 mtdcr hsmc1_cr0,r10
693 lis r10,0x8078 /* AUTO-REFRESH */
694 ori r10,r10,0x0000
695 mtdcr hsmc1_cr0,r10
701 lis r10,0x8070 /* PROGRAM MODE W/DATA REG VALUE */
702 ori r10,r10,0x8000
703 mtdcr hsmc1_cr0,r10
712 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */
713 ori r10,r10,0x0000
714 mtdcr hsmc1_cr1,r10
720 lis r10,0x8078 /* AUTO-REFRESH */
721 ori r10,r10,0x0000
722 mtdcr hsmc1_cr1,r10
728 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */
729 ori r10,r10,0x8000
730 mtdcr hsmc1_cr1,r10
739 lis r10,0x0FE1
740 ori r10,r10,0x0000
741 mtdcr hsmc1_crr,r10
791 mfdccr r10 /* r10 <- DCCR */
793 cmpwi r10,0x00
799 lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */
800 andis. r10,r10,0xFFF0
806 lwz r12,0(r10) /* force cache of address */
807 addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */
815 lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */
816 andis. r10,r10,0xFFF0
820 dcbf 0,r10 /* flush D-cache line */
821 addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */
829 li r10,0 /* r10 <- 0 */
830 mtdccr r10 /* disable the D-Cache */
834 li r10,0 /* r10 <- line address */
839 dccci 0,r10 /* invalidate A/B cache lns */
840 addi r10,r10,DCACHE_NBYTES /* bump to next line */
848 lis r10,DCACHE_ENABLE@h /* r10 <- D-cache enable msk*/
849 ori r10,r10,DCACHE_ENABLE@l
850 mtdccr r10
874 li r10,0 /* r10 <- lines address */
875 iccci 0,r10 /* invalidate all I-cache */
882 lis r10,ICACHE_ENABLE@h /* r10 <- I-cache enable msk*/
883 ori r10,r10,ICACHE_ENABLE@l
884 mticcr r10
924 mfdcr r10,hsmc0_cr0 /* r11 <- HSMC0 CR0 value */
930 mfdcr r10,hsmc0_cr1 /* r10 <- HSMC0 CR1 value */
936 mfdcr r10,hsmc1_cr0 /* r10 <- HSMC1 CR0 value */
942 mfdcr r10,hsmc1_cr1 /* r10 <- HSMC1 CR1 value */
950 and. r10,r10,r12 /* r10 <- HSMC CR bits 12-16*/