Lines Matching defs:reg_val
561 u32 reg_val;
607 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
608 reg_val &= ~0x7;
609 reg_val |= func;
610 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
614 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
615 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
617 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
618 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
620 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
621 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
623 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
624 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
626 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
627 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
629 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
630 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
632 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
633 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
635 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
636 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
640 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
641 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
643 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
645 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
646 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
648 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
653 u32 reg_val;
670 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
671 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
672 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
680 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
681 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
682 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
690 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
691 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
692 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
695 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
696 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
697 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
713 u32 reg_val;
721 reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
722 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
723 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
725 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
776 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
777 reg_val &= ~0x7;
778 reg_val |= func;
779 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
783 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
784 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
786 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
787 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
789 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
790 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
792 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
793 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
795 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
796 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
798 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
799 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
801 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
802 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
804 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
805 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
809 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
810 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
812 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
814 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
815 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
816 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
821 u32 reg_val;
837 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
838 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
839 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
847 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
848 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
849 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
857 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
858 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
859 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
867 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
868 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
869 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);