Lines Matching refs:uint32
52 uint32 devcontrol;
53 uint32 PAD[2];
54 uint32 biststatus;
55 uint32 wakeuplength;
56 uint32 PAD[3];
59 uint32 intstatus;
60 uint32 intmask;
61 uint32 gptimer;
62 uint32 PAD[23];
65 uint32 PAD[2];
66 uint32 enetftaddr;
67 uint32 enetftdata;
68 uint32 PAD[2];
71 uint32 emactxmaxburstlen;
72 uint32 emacrxmaxburstlen;
73 uint32 emaccontrol;
74 uint32 emacflowcontrol;
76 uint32 PAD[20];
79 uint32 intrecvlazy;
80 uint32 PAD[63];
85 uint32 PAD[116];
88 uint32 rxconfig;
89 uint32 rxmaxlength;
90 uint32 txmaxlength;
91 uint32 PAD;
92 uint32 mdiocontrol;
93 uint32 mdiodata;
94 uint32 emacintmask;
95 uint32 emacintstatus;
96 uint32 camdatalo;
97 uint32 camdatahi;
98 uint32 camcontrol;
99 uint32 enetcontrol;
100 uint32 txcontrol;
101 uint32 txwatermark;
102 uint32 mibcontrol;
103 uint32 PAD[49];
108 uint32 PAD[585];
115 #define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
116 #define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
117 #define DC_ER ((uint32)1 << 15) /* ephy reset */
118 #define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
119 #define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
129 #define WL_D0 ((uint32)1 << 7)
132 #define WL_D1 ((uint32)1 << 15)
135 #define WL_D2 ((uint32)1 << 23)
138 #define WL_D3 ((uint32)1 << 31)
141 #define I_PME ((uint32)1 << 6) /* power management event */
142 #define I_TO ((uint32)1 << 7) /* general purpose timeout */
143 #define I_PC ((uint32)1 << 10) /* descriptor error */
144 #define I_PD ((uint32)1 << 11) /* data error */
145 #define I_DE ((uint32)1 << 12) /* descriptor protocol error */
146 #define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
147 #define I_RO ((uint32)1 << 14) /* receive fifo overflow */
148 #define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
149 #define I_RI ((uint32)1 << 16) /* receive interrupt */
150 #define I_XI ((uint32)1 << 24) /* transmit interrupt */
151 #define I_EM ((uint32)1 << 26) /* emac interrupt */
152 #define I_MW ((uint32)1 << 27) /* mii write */
153 #define I_MR ((uint32)1 << 28) /* mii read */
156 #define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
157 #define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
158 #define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
164 #define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
172 #define ERC_DB ((uint32)1 << 0) /* disable broadcast */
173 #define ERC_AM ((uint32)1 << 1) /* accept all multicast */
174 #define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
175 #define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
176 #define ERC_LE ((uint32)1 << 4) /* loopback enable */
177 #define ERC_FE ((uint32)1 << 5) /* enable flow control */
178 #define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
179 #define ERC_RF ((uint32)1 << 7) /* reject filter */
180 #define ERC_CA ((uint32)1 << 8) /* cam absent */
184 #define MC_PE ((uint32)1 << 7) /* mii preamble enable */
204 #define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
205 #define EI_MIB ((uint32)1 << 1) /* mib interrupt */
206 #define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
209 #define CD_V ((uint32)1 << 16) /* valid bit */
212 #define CC_CE ((uint32)1 << 0) /* cam enable */
213 #define CC_MS ((uint32)1 << 1) /* mask select */
214 #define CC_RD ((uint32)1 << 2) /* read */
215 #define CC_WR ((uint32)1 << 3) /* write */
218 #define CC_CB ((uint32)1 << 31) /* cam busy */
221 #define EC_EE ((uint32)1 << 0) /* emac enable */
222 #define EC_ED ((uint32)1 << 1) /* emac disable */
223 #define EC_ES ((uint32)1 << 2) /* emac soft reset */
224 #define EC_EP ((uint32)1 << 3) /* external phy select */
227 #define EXC_FD ((uint32)1 << 0) /* full duplex */
228 #define EXC_FM ((uint32)1 << 1) /* flowmode */
229 #define EXC_SB ((uint32)1 << 2) /* single backoff enable */
230 #define EXC_SS ((uint32)1 << 3) /* small slottime */
233 #define EMC_RZ ((uint32)1 << 0) /* autoclear on read */