Lines Matching refs:SI_MAXCORES
69 void *regs[SI_MAXCORES]; /* other regs va */
73 uint coreid[SI_MAXCORES]; /* id of each core */
74 uint32 coresba[SI_MAXCORES]; /* backplane address of each core */
75 void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
76 uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
77 uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */
78 uint32 coresba2_size[SI_MAXCORES]; /* second address space size */
81 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
82 uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
84 uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */
85 uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */
91 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
95 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)