Lines Matching defs:CPM_IRQ_OFFSET
413 #define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
414 #define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
444 #define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
445 #define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
446 #define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
447 #define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
448 #define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
449 #define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
497 #ifndef CPM_IRQ_OFFSET
498 #define CPM_IRQ_OFFSET 0
507 #define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
562 #define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
563 #define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
564 #define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
565 #define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
566 #define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
567 #define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
568 #define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
569 #define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
570 #define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
571 #define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
572 #define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
573 #define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
574 #define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
575 #define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
576 #define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
577 #define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
578 #define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
579 #define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
580 #define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
581 #define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
582 #define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
583 #define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
584 #define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
585 #define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
586 #define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
587 #define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
588 #define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
589 #define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
590 #define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
591 #define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
592 #define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
593 #define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
594 #define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
595 #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
596 #define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
597 #define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
709 #ifndef CPM_IRQ_OFFSET
710 #define CPM_IRQ_OFFSET 0
715 #define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
716 #define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
717 #define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
718 #define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
719 #define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
720 #define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
721 #define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
722 #define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
723 #define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
724 #define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
725 #define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
726 #define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
727 #define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
728 #define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
729 #define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
730 #define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
731 #define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
732 #define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
733 #define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET)
734 #define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
735 #define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
736 #define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
737 #define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
738 #define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
739 #define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
740 #define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
741 #define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
742 #define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
743 #define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
744 #define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
745 #define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
746 #define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
747 #define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
748 #define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
749 #define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
750 #define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
751 #define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
752 #define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
753 #define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
754 #define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
755 #define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
756 #define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
757 #define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
758 #define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
759 #define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
760 #define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
761 #define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
762 #define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
763 #define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
764 #define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
765 #define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)