Lines Matching defs:dbri
7 * Based entirely upon drivers/sbus/audio/dbri.c which is:
308 void __iomem *regs; /* dbri HW regs */
569 #define DBRI_STREAM(dbri, substream) \
570 &dbri->stream_info[DBRI_STREAMNO(substream)]
623 dbri->dma->cmd buffer. After this, the commands can be written to
633 static void dbri_cmdwait(struct snd_dbri *dbri)
639 spin_lock_irqsave(&dbri->lock, flags);
640 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
641 spin_unlock_irqrestore(&dbri->lock, flags);
643 spin_lock_irqsave(&dbri->lock, flags);
645 spin_unlock_irqrestore(&dbri->lock, flags);
657 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
661 spin_lock(&dbri->cmdlock);
662 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
663 return dbri->cmdptr + 2;
664 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
665 return dbri->dma->cmd;
680 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
691 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
692 *(dbri->cmdptr+1) = addr;
693 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
696 if (cmd > dbri->cmdptr) {
699 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
703 s32 *ptr = dbri->cmdptr;
708 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
715 tmp = sbus_readl(dbri->regs + REG0);
717 sbus_writel(tmp, dbri->regs + REG0);
719 dbri->cmdptr = cmd;
720 spin_unlock(&dbri->cmdlock);
724 static void dbri_reset(struct snd_dbri *dbri)
730 sbus_readl(dbri->regs + REG0),
731 sbus_readl(dbri->regs + REG2),
732 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
734 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
735 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
740 tmp = sbus_readl(dbri->regs + REG0);
743 sbus_writel(tmp, dbri->regs + REG0);
747 static void __devinit dbri_initialize(struct snd_dbri *dbri)
754 spin_lock_irqsave(&dbri->lock, flags);
756 dbri_reset(dbri);
760 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
762 spin_lock_init(&dbri->cmdlock);
766 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
767 dbri->dma->intr[0] = dma_addr;
768 dbri->dbri_irqp = 1;
772 spin_lock(&dbri->cmdlock);
773 cmd = dbri->cmdptr = dbri->dma->cmd;
777 dbri->cmdptr = cmd;
780 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
781 sbus_writel(dma_addr, dbri->regs + REG8);
782 spin_unlock(&dbri->cmdlock);
784 spin_unlock_irqrestore(&dbri->lock, flags);
785 dbri_cmdwait(dbri);
802 static inline int pipe_active(struct snd_dbri *dbri, int pipe)
804 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
807 /* reset_pipe(dbri, pipe)
812 static void reset_pipe(struct snd_dbri *dbri, int pipe)
824 sdp = dbri->pipes[pipe].sdp;
831 cmd = dbri_cmdlock(dbri, 3);
835 dbri_cmdsend(dbri, cmd, 3);
837 desc = dbri->pipes[pipe].first_desc;
840 dbri->dma->desc[desc].ba = 0;
841 dbri->dma->desc[desc].nda = 0;
842 desc = dbri->next_desc[desc];
843 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
845 dbri->pipes[pipe].desc = -1;
846 dbri->pipes[pipe].first_desc = -1;
852 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
873 dbri->pipes[pipe].sdp = sdp;
874 dbri->pipes[pipe].desc = -1;
875 dbri->pipes[pipe].first_desc = -1;
877 reset_pipe(dbri, pipe);
883 static void link_time_slot(struct snd_dbri *dbri, int pipe,
898 if (dbri->pipes[pipe].sdp == 0
899 || dbri->pipes[prevpipe].sdp == 0
900 || dbri->pipes[nextpipe].sdp == 0) {
906 dbri->pipes[prevpipe].nextpipe = pipe;
907 dbri->pipes[pipe].nextpipe = nextpipe;
908 dbri->pipes[pipe].length = length;
910 cmd = dbri_cmdlock(dbri, 4);
912 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
919 cycle = dbri->chi_bpf;
935 dbri_cmdsend(dbri, cmd, 4);
955 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
965 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
971 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
976 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
984 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
985 data = reverse_bytes(data, dbri->pipes[pipe].length);
987 cmd = dbri_cmdlock(dbri, 3);
993 spin_lock_irqsave(&dbri->lock, flags);
994 dbri_cmdsend(dbri, cmd, 3);
995 spin_unlock_irqrestore(&dbri->lock, flags);
996 dbri_cmdwait(dbri);
1000 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1008 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1014 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1020 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1039 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1041 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1053 if (dbri->pipes[info->pipe].sdp == 0) {
1063 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1069 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1078 if (pipe_active(dbri, info->pipe)) {
1089 desc = dbri->pipes[info->pipe].first_desc;
1092 dbri->dma->desc[desc].ba = 0;
1093 dbri->dma->desc[desc].nda = 0;
1094 desc = dbri->next_desc[desc];
1096 desc != dbri->pipes[info->pipe].first_desc);
1098 dbri->pipes[info->pipe].desc = -1;
1099 dbri->pipes[info->pipe].first_desc = -1;
1106 if (!dbri->dma->desc[desc].ba)
1123 dbri->next_desc[desc] = -1;
1124 dbri->dma->desc[desc].ba = dvma_buffer;
1125 dbri->dma->desc[desc].nda = 0;
1128 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1129 dbri->dma->desc[desc].word4 = 0;
1130 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1132 dbri->dma->desc[desc].word1 = 0;
1133 dbri->dma->desc[desc].word4 =
1140 dbri->next_desc[last_desc] = desc;
1141 dbri->dma->desc[last_desc].nda =
1142 dbri->dma_dvma + dbri_dma_off(desc, desc);
1156 dbri->dma->desc[last_desc].nda =
1157 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1158 dbri->next_desc[last_desc] = first_desc;
1159 dbri->pipes[info->pipe].first_desc = first_desc;
1160 dbri->pipes[info->pipe].desc = first_desc;
1166 dbri->dma->desc[desc].word1,
1167 dbri->dma->desc[desc].ba,
1168 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1169 desc = dbri->next_desc[desc];
1193 static void reset_chi(struct snd_dbri *dbri,
1202 cmd = dbri_cmdlock(dbri, 4);
1209 dbri_cmdsend(dbri, cmd, 4);
1211 dbri->pipes[16].sdp = 1;
1212 dbri->pipes[16].nextpipe = 16;
1214 cmd = dbri_cmdlock(dbri, 4);
1242 dbri->chi_bpf = bits_per_frame;
1256 dbri_cmdsend(dbri, cmd, 4);
1270 static __devinit void cs4215_setup_pipes(struct snd_dbri *dbri)
1274 spin_lock_irqsave(&dbri->lock, flags);
1290 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1291 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1292 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1293 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1295 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1296 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1297 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1298 spin_unlock_irqrestore(&dbri->lock, flags);
1300 dbri_cmdwait(dbri);
1337 static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1340 dbri->mm.data[0] |= 63;
1341 dbri->mm.data[1] |= 63;
1342 dbri->mm.data[2] &= ~15;
1343 dbri->mm.data[3] &= ~15;
1346 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1350 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1351 dbri->mm.data[1] &= ~0x3f;
1352 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1353 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1356 info = &dbri->stream_info[DBRI_REC];
1359 dbri->mm.data[2] |= CS4215_LG(left_gain);
1360 dbri->mm.data[3] |= CS4215_RG(right_gain);
1363 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1369 static void cs4215_open(struct snd_dbri *dbri)
1376 dbri->mm.channels, dbri->mm.precision);
1382 cs4215_setdata(dbri, 1);
1398 spin_lock_irqsave(&dbri->lock, flags);
1399 tmp = sbus_readl(dbri->regs + REG0);
1401 sbus_writel(tmp, dbri->regs + REG0);
1405 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1407 reset_chi(dbri, CHIslave, 128);
1415 data_width = dbri->mm.channels * dbri->mm.precision;
1417 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1418 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1419 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1420 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1422 tmp = sbus_readl(dbri->regs + REG0);
1424 sbus_writel(tmp, dbri->regs + REG0);
1425 spin_unlock_irqrestore(&dbri->lock, flags);
1427 cs4215_setdata(dbri, 0);
1433 static int cs4215_setctrl(struct snd_dbri *dbri)
1443 cs4215_setdata(dbri, 1);
1450 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1451 sbus_writel(val, dbri->regs + REG2);
1473 spin_lock_irqsave(&dbri->lock, flags);
1474 tmp = sbus_readl(dbri->regs + REG0);
1476 sbus_writel(tmp, dbri->regs + REG0);
1478 reset_chi(dbri, CHImaster, 128);
1487 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1488 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1489 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1490 spin_unlock_irqrestore(&dbri->lock, flags);
1493 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1494 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1496 spin_lock_irqsave(&dbri->lock, flags);
1497 tmp = sbus_readl(dbri->regs + REG0);
1499 sbus_writel(tmp, dbri->regs + REG0);
1500 spin_unlock_irqrestore(&dbri->lock, flags);
1502 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1507 dbri->mm.status);
1514 recv_fixed(dbri, 19, NULL);
1519 dbri->mm.ctrl[0] |= CS4215_CLB;
1520 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1525 cs4215_setdata(dbri, 0);
1536 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1554 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1555 dbri->mm.precision = 8;
1558 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1559 dbri->mm.precision = 8;
1562 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1563 dbri->mm.precision = 8;
1566 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1567 dbri->mm.precision = 16;
1575 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1576 dbri->mm.ctrl[2] = CS4215_XCLK |
1579 dbri->mm.channels = channels;
1581 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1583 ret = cs4215_setctrl(dbri);
1585 cs4215_open(dbri); /* set codec to data mode */
1593 static __devinit int cs4215_init(struct snd_dbri *dbri)
1595 u32 reg2 = sbus_readl(dbri->regs + REG2);
1601 dbri->mm.onboard = 1;
1605 dbri->mm.onboard = 0;
1610 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1619 cs4215_setup_pipes(dbri);
1620 cs4215_init_data(&dbri->mm);
1623 recv_fixed(dbri, 18, &dbri->mm.status);
1624 recv_fixed(dbri, 19, &dbri->mm.version);
1626 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1627 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1629 dbri->mm.offset);
1632 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1657 static void xmit_descs(struct snd_dbri *dbri)
1664 if (dbri == NULL)
1667 info = &dbri->stream_info[DBRI_REC];
1668 spin_lock_irqsave(&dbri->lock, flags);
1671 first_td = dbri->pipes[info->pipe].first_desc;
1677 cmd = dbri_cmdlock(dbri, 2);
1679 dbri->pipes[info->pipe].sdp
1681 *(cmd++) = dbri->dma_dvma +
1683 dbri_cmdsend(dbri, cmd, 2);
1686 dbri->pipes[info->pipe].desc = first_td;
1690 info = &dbri->stream_info[DBRI_PLAY];
1693 first_td = dbri->pipes[info->pipe].first_desc;
1699 cmd = dbri_cmdlock(dbri, 2);
1701 dbri->pipes[info->pipe].sdp
1703 *(cmd++) = dbri->dma_dvma +
1705 dbri_cmdsend(dbri, cmd, 2);
1708 dbri->pipes[info->pipe].desc = first_td;
1712 spin_unlock_irqrestore(&dbri->lock, flags);
1729 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1731 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1732 int td = dbri->pipes[pipe].desc;
1741 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1747 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1748 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1750 td = dbri->next_desc[td];
1751 dbri->pipes[pipe].desc = td;
1755 spin_unlock(&dbri->lock);
1757 spin_lock(&dbri->lock);
1760 static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1763 int rd = dbri->pipes[pipe].desc;
1771 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1772 status = dbri->dma->desc[rd].word1;
1773 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1775 info = &dbri->stream_info[DBRI_REC];
1783 spin_unlock(&dbri->lock);
1785 spin_lock(&dbri->lock);
1788 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1812 reception_complete_intr(dbri, channel);
1816 transmission_complete_intr(dbri, channel);
1828 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1829 val = reverse_bytes(val, dbri->pipes[channel].length);
1831 if (dbri->pipes[channel].recv_fixed_ptr)
1832 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1846 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1850 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1851 dbri->dma->intr[dbri->dbri_irqp] = 0;
1852 dbri->dbri_irqp++;
1853 if (dbri->dbri_irqp == DBRI_INT_BLK)
1854 dbri->dbri_irqp = 1;
1856 dbri_process_one_interrupt(dbri, x);
1862 struct snd_dbri *dbri = dev_id;
1866 if (dbri == NULL)
1868 spin_lock(&dbri->lock);
1873 x = sbus_readl(dbri->regs + REG1);
1903 dbri_reset(dbri);
1905 tmp = sbus_readl(dbri->regs + REG0);
1907 sbus_writel(tmp, dbri->regs + REG0);
1911 dbri_process_interrupt_buffer(dbri);
1913 spin_unlock(&dbri->lock);
1979 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
1981 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1987 spin_lock_irqsave(&dbri->lock, flags);
1992 spin_unlock_irqrestore(&dbri->lock, flags);
2002 cs4215_open(dbri);
2009 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2010 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2023 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2024 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2029 ret = cs4215_prepare(dbri, params_rate(hw_params),
2050 dma_map_single(&dbri->op->dev,
2064 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2065 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2078 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2083 reset_pipe(dbri, info->pipe);
2092 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2093 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2102 spin_lock_irq(&dbri->lock);
2108 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2111 spin_unlock_irq(&dbri->lock);
2119 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2120 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2128 xmit_descs(dbri);
2132 reset_pipe(dbri, info->pipe);
2143 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2144 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2213 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2216 if (snd_BUG_ON(!dbri))
2218 info = &dbri->stream_info[kcontrol->private_value];
2228 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2230 &dbri->stream_info[kcontrol->private_value];
2256 cs4215_setdata(dbri, 1);
2258 cs4215_setdata(dbri, 0);
2279 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2285 if (snd_BUG_ON(!dbri))
2290 (dbri->mm.data[elem] >> shift) & mask;
2293 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2304 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2312 if (snd_BUG_ON(!dbri))
2321 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2323 changed = (val != dbri->mm.data[elem]);
2325 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2327 changed = (val != dbri->mm.ctrl[elem - 4]);
2333 dbri->mm.data[elem & 3]);
2339 cs4215_setdata(dbri, 1);
2341 cs4215_setdata(dbri, 0);
2386 struct snd_dbri *dbri;
2390 dbri = card->private_data;
2396 snd_ctl_new1(&dbri_controls[idx], dbri));
2402 dbri->stream_info[idx].left_gain = 0;
2403 dbri->stream_info[idx].right_gain = 0;
2415 struct snd_dbri *dbri = entry->private_data;
2417 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2418 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2419 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2420 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2427 struct snd_dbri *dbri = entry->private_data;
2432 if (pipe_active(dbri, pipe)) {
2433 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2449 struct snd_dbri *dbri = card->private_data;
2453 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2457 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2468 static void snd_dbri_free(struct snd_dbri *dbri);
2474 struct snd_dbri *dbri = card->private_data;
2477 spin_lock_init(&dbri->lock);
2478 dbri->op = op;
2479 dbri->irq = irq;
2481 dbri->dma = dma_alloc_coherent(&op->dev,
2483 &dbri->dma_dvma, GFP_ATOMIC);
2484 if (!dbri->dma)
2486 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2489 dbri->dma, dbri->dma_dvma);
2492 dbri->regs_size = resource_size(&op->resource[0]);
2493 dbri->regs = of_ioremap(&op->resource[0], 0,
2494 dbri->regs_size, "DBRI Registers");
2495 if (!dbri->regs) {
2498 (void *)dbri->dma, dbri->dma_dvma);
2502 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2503 "DBRI audio", dbri);
2505 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2506 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2508 (void *)dbri->dma, dbri->dma_dvma);
2513 dbri_initialize(dbri);
2514 err = cs4215_init(dbri);
2516 snd_dbri_free(dbri);
2523 static void snd_dbri_free(struct snd_dbri *dbri)
2526 dbri_reset(dbri);
2528 if (dbri->irq)
2529 free_irq(dbri->irq, dbri);
2531 if (dbri->regs)
2532 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2534 if (dbri->dma)
2535 dma_free_coherent(&dbri->op->dev,
2537 (void *)dbri->dma, dbri->dma_dvma);
2542 struct snd_dbri *dbri;
2580 dbri = card->private_data;
2598 dev, dbri->regs,
2599 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2605 snd_dbri_free(dbri);
2636 .name = "dbri",
2644 /* Probe for the dbri chip and then attach the driver. */