Lines Matching refs:rirb
421 struct azx_rb rirb;
556 chip->rirb.addr = chip->rb.addr + 2048;
557 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
558 chip->rirb.wp = chip->rirb.rp = 0;
559 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
560 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
561 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
563 /* set the rirb size to 256 entries (ULI requires explicitly) */
565 /* reset the rirb hw write pointer */
572 /* enable rirb dma and response irq */
624 chip->rirb.cmds[addr]++;
643 if (wp == chip->rirb.wp)
645 chip->rirb.wp = wp;
647 while (chip->rirb.rp != wp) {
648 chip->rirb.rp++;
649 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
651 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
652 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
653 res = le32_to_cpu(chip->rirb.buf[rp]);
657 else if (chip->rirb.cmds[addr]) {
658 chip->rirb.res[addr] = res;
660 chip->rirb.cmds[addr]--;
685 if (!chip->rirb.cmds[addr]) {
691 return chip->rirb.res[addr]; /* the last value */
783 /* reuse rirb.res as the response return value */
784 chip->rirb.res[addr] = azx_readl(chip, IR);
792 chip->rirb.res[addr] = -1;
828 return chip->rirb.res[addr];
966 /* clear rirb status */
1141 /* clear rirb int */