Lines Matching refs:azx_dev
336 struct azx_dev {
408 struct azx_dev *azx_dev;
939 struct azx_dev *azx_dev = &chip->azx_dev[i];
940 azx_sd_writeb(azx_dev, SD_CTL,
941 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
959 struct azx_dev *azx_dev = &chip->azx_dev[i];
960 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
974 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
979 azx_dev->insufficient = 1;
983 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
985 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
990 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
992 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
994 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
998 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1000 azx_stream_clear(chip, azx_dev);
1003 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1096 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1104 struct azx_dev *azx_dev;
1118 azx_dev = &chip->azx_dev[i];
1119 if (status & azx_dev->sd_int_sta_mask) {
1120 sd_status = azx_sd_readb(azx_dev, SD_STS);
1121 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1122 if (!azx_dev->substream || !azx_dev->running ||
1126 ok = azx_position_ok(chip, azx_dev);
1128 azx_dev->irq_pending = 0;
1130 snd_pcm_period_elapsed(azx_dev->substream);
1134 azx_dev->irq_pending = 1;
1162 struct azx_dev *azx_dev, u32 **bdlp,
1171 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1187 azx_dev->frags++;
1199 struct azx_dev *azx_dev)
1206 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1207 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1209 period_bytes = azx_dev->period_bytes;
1210 periods = azx_dev->bufsize / period_bytes;
1213 bdl = (u32 *)azx_dev->bdl.area;
1215 azx_dev->frags = 0;
1232 ofs = setup_bdle(substream, azx_dev,
1241 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1244 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1253 azx_dev->bufsize, period_bytes);
1258 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1263 azx_stream_clear(chip, azx_dev);
1265 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1269 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1273 azx_sd_writeb(azx_dev, SD_CTL, val);
1278 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1283 *azx_dev->posbuf = 0;
1289 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1292 azx_stream_clear(chip, azx_dev);
1294 azx_sd_writel(azx_dev, SD_CTL,
1295 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1296 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1299 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1303 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1306 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1310 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1312 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1326 azx_sd_writel(azx_dev, SD_CTL,
1327 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1476 static inline struct azx_dev *
1480 struct azx_dev *res = NULL;
1490 if (!chip->azx_dev[dev].opened) {
1491 res = &chip->azx_dev[dev];
1503 static inline void azx_release_device(struct azx_dev *azx_dev)
1505 azx_dev->opened = 0;
1542 struct azx_dev *azx_dev;
1548 azx_dev = azx_assign_device(chip, substream);
1549 if (azx_dev == NULL) {
1567 azx_release_device(azx_dev);
1578 azx_release_device(azx_dev);
1585 azx_dev->substream = substream;
1586 azx_dev->running = 0;
1589 runtime->private_data = azx_dev;
1600 struct azx_dev *azx_dev = get_azx_dev(substream);
1605 azx_dev->substream = NULL;
1606 azx_dev->running = 0;
1608 azx_release_device(azx_dev);
1618 struct azx_dev *azx_dev = get_azx_dev(substream);
1620 azx_dev->bufsize = 0;
1621 azx_dev->period_bytes = 0;
1622 azx_dev->format_val = 0;
1630 struct azx_dev *azx_dev = get_azx_dev(substream);
1634 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1635 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1636 azx_sd_writel(azx_dev, SD_CTL, 0);
1637 azx_dev->bufsize = 0;
1638 azx_dev->period_bytes = 0;
1639 azx_dev->format_val = 0;
1650 struct azx_dev *azx_dev = get_azx_dev(substream);
1656 azx_stream_reset(chip, azx_dev);
1675 if (bufsize != azx_dev->bufsize ||
1676 period_bytes != azx_dev->period_bytes ||
1677 format_val != azx_dev->format_val) {
1678 azx_dev->bufsize = bufsize;
1679 azx_dev->period_bytes = period_bytes;
1680 azx_dev->format_val = format_val;
1681 err = azx_setup_periods(chip, substream, azx_dev);
1687 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1689 azx_setup_controller(chip, azx_dev);
1691 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1693 azx_dev->fifo_size = 0;
1695 stream_tag = azx_dev->stream_tag;
1701 azx_dev->format_val, substream);
1708 struct azx_dev *azx_dev;
1732 azx_dev = get_azx_dev(s);
1733 sbits |= 1 << azx_dev->index;
1746 azx_dev = get_azx_dev(s);
1748 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1750 azx_dev->start_wallclk -=
1751 azx_dev->period_wallclk;
1752 azx_stream_start(chip, azx_dev);
1754 azx_stream_stop(chip, azx_dev);
1756 azx_dev->running = start;
1768 azx_dev = get_azx_dev(s);
1769 if (!(azx_sd_readb(azx_dev, SD_STS) &
1784 azx_dev = get_azx_dev(s);
1785 if (azx_sd_readb(azx_dev, SD_CTL) &
1805 struct azx_dev *azx_dev)
1811 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1812 if (azx_dev->index >= 4) {
1821 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1822 mod_dma_pos %= azx_dev->period_bytes;
1824 /* azx_dev->fifo_size can't get FIFO size of in stream.
1829 if (azx_dev->insufficient) {
1834 azx_dev->insufficient = 0;
1838 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1843 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1844 mod_link_pos = link_pos % azx_dev->period_bytes;
1850 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1851 if (bound_pos >= azx_dev->bufsize)
1860 struct azx_dev *azx_dev)
1865 pos = azx_via_get_position(chip, azx_dev);
1867 int stream = azx_dev->substream->stream;
1871 pos = le32_to_cpu(*azx_dev->posbuf);
1874 pos = azx_sd_readl(azx_dev, SD_LPIB);
1877 if (pos >= azx_dev->bufsize)
1886 struct azx_dev *azx_dev = get_azx_dev(substream);
1888 azx_get_position(chip, azx_dev));
1900 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1906 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1907 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1910 stream = azx_dev->substream->stream;
1911 pos = azx_get_position(chip, azx_dev);
1918 pos = azx_get_position(chip, azx_dev);
1923 if (WARN_ONCE(!azx_dev->period_bytes,
1924 "hda-intel: zero azx_dev->period_bytes"))
1926 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1927 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1930 azx_dev->start_wallclk += wallclk;
1954 struct azx_dev *azx_dev = &chip->azx_dev[i];
1955 if (!azx_dev->irq_pending ||
1956 !azx_dev->substream ||
1957 !azx_dev->running)
1959 ok = azx_position_ok(chip, azx_dev);
1961 azx_dev->irq_pending = 0;
1963 snd_pcm_period_elapsed(azx_dev->substream);
1984 chip->azx_dev[i].irq_pending = 0;
2079 struct azx_dev *azx_dev = &chip->azx_dev[i];
2080 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2082 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2084 azx_dev->sd_int_sta_mask = 1 << i;
2086 azx_dev->index = i;
2087 azx_dev->stream_tag = i + 1;
2258 azx_stream_stop(chip, &chip->azx_dev[i]);
2269 if (chip->azx_dev) {
2271 if (chip->azx_dev[i].bdl.area)
2272 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2280 kfree(chip->azx_dev);
2584 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2586 if (!chip->azx_dev) {
2587 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2595 BDL_SIZE, &chip->azx_dev[i].bdl);