Lines Matching refs:ct
254 if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
256 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
258 /*aty_calc_pll_ct(info, &pll->ct);*/
266 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
268 if(pll->ct.xres > 0) {
270 ret /= pll->ct.xres;
290 pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
294 par->clk_wr_offset, pll->ct.vclk_fb_div,
295 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
312 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
318 tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
325 tmp |= pll->ct.pll_ext_cntl;
330 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
332 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
335 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
338 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
339 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
357 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
358 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
383 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
385 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
386 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
387 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
388 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
390 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
391 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
394 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
395 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
409 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
410 pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
411 pll->ct.xclk_ref_div = 1;
412 switch (pll->ct.xclk_post_div) {
417 pll->ct.xclk_ref_div = 3;
418 pll->ct.xclk_post_div = 0;
422 printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
425 pll->ct.mclk_fb_mult = 2;
426 if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
427 pll->ct.mclk_fb_mult = 4;
428 pll->ct.xclk_post_div -= 1;
433 __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
439 pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
440 pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
443 pll->ct.fifo_size = 32;
445 pll->ct.fifo_size = 24;
446 pll->ct.xclkpagefaultdelay += 2;
447 pll->ct.xclkmaxrasdelay += 3;
453 pll->ct.dsp_loop_latency = 10;
455 pll->ct.dsp_loop_latency = 8;
456 pll->ct.xclkpagefaultdelay += 2;
462 pll->ct.dsp_loop_latency = 9;
464 pll->ct.dsp_loop_latency = 8;
465 pll->ct.xclkpagefaultdelay += 1;
470 pll->ct.dsp_loop_latency = 11;
472 pll->ct.dsp_loop_latency = 10;
473 pll->ct.xclkpagefaultdelay += 1;
477 pll->ct.dsp_loop_latency = 8;
478 pll->ct.xclkpagefaultdelay += 3;
481 pll->ct.dsp_loop_latency = 11;
482 pll->ct.xclkpagefaultdelay += 3;
486 if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
487 pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
496 pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
501 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
503 pll->ct.xclk_post_div_real = postdividers[pll_ext_cntl & 0x07];
507 pll->ct.mclk_fb_div = mclk_fb_div;
511 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
513 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
514 (pll->ct.mclk_fb_mult * par->xclk_per);
524 pll->ct.xclk_post_div_real = postdividers[xpost_div];
525 pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
530 pll->ct.xclk_post_div = xpost_div;
531 pll->ct.xclk_ref_div = 1;
536 pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
537 (par->ref_clk_per * pll->ct.pll_ref_div);
539 __func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
543 pll->ct.pll_gen_cntl = OSC_EN;
545 pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
548 pll->ct.pll_ext_cntl = 0;
550 pll->ct.pll_ext_cntl = xpost_div;
552 if (pll->ct.mclk_fb_mult == 4)
553 pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
556 pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
562 pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
564 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
574 pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
575 pll->ct.spll_cntl2 = mpost_div << 4;
577 pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
578 (par->ref_clk_per * pll->ct.pll_ref_div);
585 pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
586 pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
604 aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
605 aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
613 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
614 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
615 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
616 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
617 aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);