Lines Matching defs:pll
17 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
18 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
19 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
20 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
119 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll)
126 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
129 ras_multiplier = pll->xclkmaxrasdelay;
135 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */
141 if (pll->xres != 0) {
145 divider = divider * pll->xres & ~7;
148 ras_divider = ras_divider * pll->xres & ~7;
159 tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
172 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
183 dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift);
199 pll->dsp_on_off = (dsp_on << 16) + dsp_off;
200 pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks;
203 __func__, pll->dsp_config, pll->dsp_on_off);
208 static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll)
214 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
219 pll->vclk_post_div = (q < 128*8);
220 pll->vclk_post_div += (q < 64*8);
221 pll->vclk_post_div += (q < 32*8);
223 pll->vclk_post_div_real = postdividers[pll->vclk_post_div];
224 // pll->vclk_post_div <<= 6;
225 pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
226 pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
227 (par->ref_clk_per * pll->pll_ref_div);
230 __func__, pllvclk, pllvclk / pll->vclk_post_div_real);
232 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
236 int ecp = pllvclk / pll->vclk_post_div_real;
243 pll->pll_vclk_cntl |= ecp_div << 4;
249 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll)
254 if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
256 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
258 /*aty_calc_pll_ct(info, &pll->ct);*/
262 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll)
266 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
268 if(pll->ct.xres > 0) {
270 ret /= pll->ct.xres;
279 void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll)
290 pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
294 par->clk_wr_offset, pll->ct.vclk_fb_div,
295 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
312 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
318 tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
325 tmp |= pll->ct.pll_ext_cntl;
330 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
332 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
335 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
338 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
339 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
357 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
358 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
376 union aty_pll *pll)
383 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
385 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
386 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
387 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
388 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
390 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
391 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
394 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
395 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
400 union aty_pll *pll)
409 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
410 pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
411 pll->ct.xclk_ref_div = 1;
412 switch (pll->ct.xclk_post_div) {
417 pll->ct.xclk_ref_div = 3;
418 pll->ct.xclk_post_div = 0;
422 printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
425 pll->ct.mclk_fb_mult = 2;
426 if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
427 pll->ct.mclk_fb_mult = 4;
428 pll->ct.xclk_post_div -= 1;
433 __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
439 pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
440 pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
443 pll->ct.fifo_size = 32;
445 pll->ct.fifo_size = 24;
446 pll->ct.xclkpagefaultdelay += 2;
447 pll->ct.xclkmaxrasdelay += 3;
453 pll->ct.dsp_loop_latency = 10;
455 pll->ct.dsp_loop_latency = 8;
456 pll->ct.xclkpagefaultdelay += 2;
462 pll->ct.dsp_loop_latency = 9;
464 pll->ct.dsp_loop_latency = 8;
465 pll->ct.xclkpagefaultdelay += 1;
470 pll->ct.dsp_loop_latency = 11;
472 pll->ct.dsp_loop_latency = 10;
473 pll->ct.xclkpagefaultdelay += 1;
477 pll->ct.dsp_loop_latency = 8;
478 pll->ct.xclkpagefaultdelay += 3;
481 pll->ct.dsp_loop_latency = 11;
482 pll->ct.xclkpagefaultdelay += 3;
486 if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
487 pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
496 pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
501 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
503 pll->ct.xclk_post_div_real = postdividers[pll_ext_cntl & 0x07];
507 pll->ct.mclk_fb_div = mclk_fb_div;
511 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
513 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
514 (pll->ct.mclk_fb_mult * par->xclk_per);
524 pll->ct.xclk_post_div_real = postdividers[xpost_div];
525 pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
530 pll->ct.xclk_post_div = xpost_div;
531 pll->ct.xclk_ref_div = 1;
536 pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
537 (par->ref_clk_per * pll->ct.pll_ref_div);
539 __func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
543 pll->ct.pll_gen_cntl = OSC_EN;
545 pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
548 pll->ct.pll_ext_cntl = 0;
550 pll->ct.pll_ext_cntl = xpost_div;
552 if (pll->ct.mclk_fb_mult == 4)
553 pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
556 pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
562 pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
564 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
574 pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
575 pll->ct.spll_cntl2 = mpost_div << 4;
577 pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
578 (par->ref_clk_per * pll->ct.pll_ref_div);
585 pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
586 pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
592 union aty_pll *pll)
604 aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
605 aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
613 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
614 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
615 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
616 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
617 aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);