Lines Matching defs:set
46 * MPS is set to 64.
321 /* set FIFO sizes to 2048/1024 */
330 * that if the settings have been changed, then they are set to
761 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
766 /* set these, it seems that DMA support increments past the end
773 /* set these anyway, we may need them for non-periodic in */
1058 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1062 __func__, set ? "SET" : "CLEAR");
1074 s3c_hsotg_ep_sethalt(&ep->ep, set);
1291 /* only replace the status if we've not already set an error
1448 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1637 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1923 * endpoint, so set the endpoints to a default value. */
2159 * set. */
2273 /* set the NAK status on the endpoint, otherwise we might try and
2276 * size register hasn't been set.
2284 /* default, set to non-periodic */
2322 /* for non control endpoints, set PID to D0 */
2575 * set configuration. */
2579 /* set the PLL on, remove the HNP/SRP and set the PHY */
2648 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2651 /* set to read 1 8byte packet */
2783 /* if we're using dma, we need to set the next-endpoint pointer
2798 * Power up the phy, set the basic configuration and start the PHY.
2831 /* issue a full set of resets to the otg and core */
2872 /* set the PLL on, remove the HNP/SRP and set the PHY */
3210 * s3c_hsotg_gate - set the hardware gate for the block