Lines Matching defs:stat
432 union cvmx_spxx_clk_stat stat;
448 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
449 if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) {
455 cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
456 stat.s.s4clk0 = 0;
457 stat.s.s4clk1 = 0;
463 } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0);
473 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
474 if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) {
480 cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
481 stat.s.d4clk0 = 0;
482 stat.s.d4clk1 = 0;
488 } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0);
510 union cvmx_spxx_clk_stat stat;
547 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
548 if (stat.s.srxtrn && rx_training_needed) {
550 cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
551 stat.s.srxtrn = 0;
557 } while (stat.s.srxtrn == 0);
595 union cvmx_spxx_clk_stat stat;
608 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
613 } while (stat.s.stxcal == 0);