wireless/rt2x00/rt2500usb.c

162 		rt2x00_set_field16(&reg, PHY_CSR7_DATA, value);
163 		rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
164 		rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 0);
189 		rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
190 		rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 1);
216 		rt2x00_set_field16(&reg, PHY_CSR9_RF_VALUE, value);
220 		rt2x00_set_field16(&reg, PHY_CSR10_RF_VALUE, value >> 16);
221 		rt2x00_set_field16(&reg, PHY_CSR10_RF_NUMBER_OF_BITS, 20);
222 		rt2x00_set_field16(&reg, PHY_CSR10_RF_IF_SELECT, 0);
223 		rt2x00_set_field16(&reg, PHY_CSR10_RF_BUSY, 1);
301 		rt2x00_set_field16(&reg, MAC_CSR20_LINK, enabled);
303 		rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, enabled);
317 	rt2x00_set_field16(&reg, MAC_CSR21_ON_PERIOD, *delay_on);
318 	rt2x00_set_field16(&reg, MAC_CSR21_OFF_PERIOD, *delay_off);
408 	rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, crypto->cipher);
409 	rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
416 	rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, mask);
434 	rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CRC,
436 	rt2x00_set_field16(&reg, TXRX_CSR2_DROP_PHYSICAL,
438 	rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CONTROL,
440 	rt2x00_set_field16(&reg, TXRX_CSR2_DROP_NOT_TO_ME,
442 	rt2x00_set_field16(&reg, TXRX_CSR2_DROP_TODS,
445 	rt2x00_set_field16(&reg, TXRX_CSR2_DROP_VERSION_ERROR, 1);
446 	rt2x00_set_field16(&reg, TXRX_CSR2_DROP_MULTICAST,
448 	rt2x00_set_field16(&reg, TXRX_CSR2_DROP_BROADCAST, 0);
466 		rt2x00_set_field16(&reg, TXRX_CSR20_OFFSET, bcn_preload >> 6);
467 		rt2x00_set_field16(&reg, TXRX_CSR20_BCN_EXPECT_WINDOW,
475 		rt2x00_set_field16(&reg, TXRX_CSR18_OFFSET, 0);
479 		rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
480 		rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync);
481 		rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
500 	rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE,
507 	rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL, erp->beacon_int * 4);
541 		rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 1);
542 		rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 1);
546 		rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 0);
547 		rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 0);
552 		rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 2);
553 		rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 2);
578 		rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 1);
579 		rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 1);
587 		rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 0);
588 		rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 0);
648 		rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON,
650 		rt2x00_set_field16(&reg, MAC_CSR18_BEACONS_BEFORE_WAKEUP,
654 		rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
657 		rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1);
661 		rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
742 	rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
749 	rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 1);
750 	rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 1);
751 	rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
755 	rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
756 	rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
757 	rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
761 	rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0, 13);
762 	rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0_VALID, 1);
763 	rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1, 12);
764 	rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1_VALID, 1);
768 	rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0, 10);
769 	rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0_VALID, 1);
770 	rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1, 11);
771 	rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1_VALID, 1);
775 	rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0, 7);
776 	rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0_VALID, 1);
777 	rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1, 6);
778 	rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1_VALID, 1);
782 	rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0, 5);
783 	rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0_VALID, 1);
784 	rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1, 0);
785 	rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1_VALID, 0);
789 	rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
790 	rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, 0);
791 	rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
792 	rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
802 	rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
803 	rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
804 	rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 1);
809 		rt2x00_set_field16(&reg, PHY_CSR2_LNA, 0);
812 		rt2x00_set_field16(&reg, PHY_CSR2_LNA, 1);
813 		rt2x00_set_field16(&reg, PHY_CSR2_LNA_MODE, 3);
823 	rt2x00_set_field16(&reg, MAC_CSR8_MAX_FRAME_UNIT,
828 	rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, CIPHER_NONE);
829 	rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
830 	rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0);
834 	rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON, 90);
838 	rt2x00_set_field16(&reg, PHY_CSR4_LOW_RF_LE, 1);
842 	rt2x00_set_field16(&reg, TXRX_CSR1_AUTO_SEQUENCE, 1);
928 	rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX,
972 	rt2x00_set_field16(&reg, MAC_CSR17_BBP_DESIRE_STATE, state);
973 	rt2x00_set_field16(&reg, MAC_CSR17_RF_DESIRE_STATE, state);
974 	rt2x00_set_field16(&reg, MAC_CSR17_PUT_TO_SLEEP, put_to_sleep);
976 	rt2x00_set_field16(&reg, MAC_CSR17_SET_STATE, 1);
1118 	rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
1166 	rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
1167 	rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
1169 	rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
1321 		rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1322 		rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1324 		rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1326 		rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1328 		rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1329 		rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1330 		rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1337 		rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1338 		rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1339 		rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1346 		rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1354 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_THRESHOLD, 45);
1368 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCUPPER, 0x40);
1369 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
1373 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
1379 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_LOW, 0x48);
1380 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_HIGH, 0x41);
1387 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_LOW, 0x40);
1388 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_HIGH, 0x80);
1395 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_LOW, 0x40);
1396 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_HIGH, 0x50);
1403 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_LOW, 0x60);
1404 		rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_HIGH, 0x6d);