Lines Matching refs:pCap
153 struct ath9k_hw_capabilities *pCap = &ah->caps;
156 *low = pCap->low_5ghz_chan;
157 *high = pCap->high_5ghz_chan;
161 *low = pCap->low_2ghz_chan;
162 *high = pCap->high_2ghz_chan;
1556 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1561 if (entry >= pCap->keycache_size) {
1572 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1583 && entry + 64 >= pCap->keycache_size) {
1793 struct ath9k_hw_capabilities *pCap = &ah->caps;
1795 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1974 struct ath9k_hw_capabilities *pCap = &ah->caps;
2021 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2050 struct ath9k_hw_capabilities *pCap = &ah->caps;
2085 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2088 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2092 pCap->wireless_modes);
2095 pCap->wireless_modes);
2097 pCap->wireless_modes);
2103 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2107 pCap->wireless_modes);
2110 pCap->wireless_modes);
2112 pCap->wireless_modes);
2117 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2126 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2129 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2134 pCap->low_2ghz_chan = 2312;
2135 pCap->high_2ghz_chan = 2732;
2137 pCap->low_5ghz_chan = 4920;
2138 pCap->high_5ghz_chan = 6100;
2140 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2141 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2142 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2144 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2145 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2146 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2149 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2151 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2153 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2154 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2155 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2156 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2159 pCap->total_queues =
2162 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2165 pCap->keycache_size =
2168 pCap->keycache_size = AR_KEYTABLE_SIZE;
2170 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2173 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2175 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2178 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2180 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2182 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2184 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2186 pCap->num_gpio_pins = AR_NUM_GPIO;
2189 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2190 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2192 pCap->rts_aggr_limit = (8 * 1024);
2195 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2205 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2209 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2211 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2214 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2216 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2219 pCap->reg_cap =
2225 pCap->reg_cap =
2233 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2235 pCap->num_antcfg_5ghz =
2237 pCap->num_antcfg_2ghz =
2256 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2258 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2259 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2260 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2261 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2262 pCap->txs_len = sizeof(struct ar9003_txs);
2265 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2267 pCap->tx_desc_len = sizeof(struct ath_desc);
2272 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2276 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2279 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;