Lines Matching refs:sis_priv
367 struct sis900_private *sis_priv;
408 sis_priv = netdev_priv(net_dev);
411 sis_priv->pci_dev = pci_dev;
412 spin_lock_init(&sis_priv->lock);
421 sis_priv->tx_ring = (BufferDesc *)ring_space;
422 sis_priv->tx_ring_dma = ring_dma;
429 sis_priv->rx_ring = (BufferDesc *)ring_space;
430 sis_priv->rx_ring_dma = ring_dma;
438 sis_priv->msg_enable = sis900_debug;
440 sis_priv->msg_enable = SIS900_DEF_MSG;
442 sis_priv->mii_info.dev = net_dev;
443 sis_priv->mii_info.mdio_read = mdio_read;
444 sis_priv->mii_info.mdio_write = mdio_write;
445 sis_priv->mii_info.phy_id_mask = 0x1f;
446 sis_priv->mii_info.reg_num_mask = 0x1f;
449 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &(sis_priv->chipset_rev));
450 if(netif_msg_probe(sis_priv))
453 dev_name, sis_priv->chipset_rev);
456 if (sis_priv->chipset_rev == SIS630E_900_REV)
458 else if ((sis_priv->chipset_rev > 0x81) && (sis_priv->chipset_rev <= 0x90) )
460 else if (sis_priv->chipset_rev == SIS96x_900_REV)
472 if (sis_priv->chipset_rev == SIS630ET_900_REV)
486 pci_read_config_byte(dev, PCI_CLASS_REVISION, &sis_priv->host_bridge_rev);
501 if (netif_msg_probe(sis_priv) && (ret & PME_D3C) == 0)
507 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
508 sis_priv->rx_ring_dma);
510 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
511 sis_priv->tx_ring_dma);
531 struct sis900_private *sis_priv = netdev_priv(net_dev);
532 const char *dev_name = pci_name(sis_priv->pci_dev);
537 sis_priv->mii = NULL;
550 if (netif_msg_probe(sis_priv))
559 mii_phy = sis_priv->first_mii;
573 mii_phy->next = sis_priv->mii;
574 sis_priv->mii = mii_phy;
575 sis_priv->first_mii = mii_phy;
599 if (sis_priv->mii == NULL) {
605 sis_priv->mii = NULL;
609 if ((sis_priv->mii->phy_id0 == 0x001D) &&
610 ((sis_priv->mii->phy_id1&0xFFF0) == 0x8000))
611 status = sis900_reset_phy(net_dev, sis_priv->cur_phy);
613 if ((sis_priv->mii->phy_id0 == 0x0015) &&
614 ((sis_priv->mii->phy_id1&0xFFF0) == 0xF440))
615 mdio_write(net_dev, sis_priv->cur_phy, 0x0018, 0xD200);
621 poll_bit ^= (mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS) & poll_bit);
630 if (sis_priv->chipset_rev == SIS630E_900_REV) {
632 mdio_write(net_dev, sis_priv->cur_phy, MII_ANADV, 0x05e1);
633 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG1, 0x22);
634 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG2, 0xff00);
635 mdio_write(net_dev, sis_priv->cur_phy, MII_MASK, 0xffc0);
636 //mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, 0x1000);
639 if (sis_priv->mii->status & MII_STAT_LINK)
658 struct sis900_private *sis_priv = netdev_priv(net_dev);
663 for (phy=sis_priv->first_mii; phy; phy=phy->next) {
687 default_phy = sis_priv->first_mii;
689 if (sis_priv->mii != default_phy) {
690 sis_priv->mii = default_phy;
691 sis_priv->cur_phy = default_phy->phy_addr;
693 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
696 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
698 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
701 mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, status);
702 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
703 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
956 struct sis900_private *sis_priv = netdev_priv(net_dev);
963 sis630_set_eq(net_dev, sis_priv->chipset_rev);
986 sis900_check_mode(net_dev, sis_priv->mii);
990 init_timer(&sis_priv->timer);
991 sis_priv->timer.expires = jiffies + HZ;
992 sis_priv->timer.data = (unsigned long)net_dev;
993 sis_priv->timer.function = &sis900_timer;
994 add_timer(&sis_priv->timer);
1010 struct sis900_private *sis_priv = netdev_priv(net_dev);
1028 if (netif_msg_hw(sis_priv)) {
1048 struct sis900_private *sis_priv = netdev_priv(net_dev);
1052 sis_priv->tx_full = 0;
1053 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1056 sis_priv->tx_skbuff[i] = NULL;
1058 sis_priv->tx_ring[i].link = sis_priv->tx_ring_dma +
1060 sis_priv->tx_ring[i].cmdsts = 0;
1061 sis_priv->tx_ring[i].bufptr = 0;
1065 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1066 if (netif_msg_hw(sis_priv))
1082 struct sis900_private *sis_priv = netdev_priv(net_dev);
1086 sis_priv->cur_rx = 0;
1087 sis_priv->dirty_rx = 0;
1091 sis_priv->rx_skbuff[i] = NULL;
1093 sis_priv->rx_ring[i].link = sis_priv->rx_ring_dma +
1095 sis_priv->rx_ring[i].cmdsts = 0;
1096 sis_priv->rx_ring[i].bufptr = 0;
1110 sis_priv->rx_skbuff[i] = skb;
1111 sis_priv->rx_ring[i].cmdsts = RX_BUF_SIZE;
1112 sis_priv->rx_ring[i].bufptr = pci_map_single(sis_priv->pci_dev,
1115 sis_priv->dirty_rx = (unsigned int) (i - NUM_RX_DESC);
1118 outl(sis_priv->rx_ring_dma, ioaddr + rxdp);
1119 if (netif_msg_hw(sis_priv))
1127 struct sis900_private *sis_priv = netdev_priv(net_dev);
1136 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1137 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1141 sis_priv->cur_phy, MII_RESV)) >> 3;
1163 (sis_priv->host_bridge_rev == SIS630B0 ||
1164 sis_priv->host_bridge_rev == SIS630B1)) {
1171 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1174 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV, reg14h);
1176 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1178 (sis_priv->host_bridge_rev == SIS630B0 ||
1179 sis_priv->host_bridge_rev == SIS630B1))
1180 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1183 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1199 struct sis900_private *sis_priv = netdev_priv(net_dev);
1200 struct mii_phy *mii_phy = sis_priv->mii;
1204 if (!sis_priv->autong_complete){
1210 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1214 sis_priv->timer.expires = jiffies + HZ;
1215 add_timer(&sis_priv->timer);
1219 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1220 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1227 mii_phy = sis_priv->mii;
1237 if(netif_msg_link(sis_priv))
1243 sis900_reset_phy(net_dev, sis_priv->cur_phy);
1245 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1251 sis_priv->timer.expires = jiffies + next_tick;
1252 add_timer(&sis_priv->timer);
1269 struct sis900_private *sis_priv = netdev_priv(net_dev);
1276 sis900_auto_negotiate(net_dev, sis_priv->cur_phy);
1282 sis_priv->autong_complete = 1;
1348 struct sis900_private *sis_priv = netdev_priv(net_dev);
1356 if(netif_msg_link(sis_priv))
1358 sis_priv->autong_complete = 1;
1366 sis_priv->autong_complete = 0;
1383 struct sis900_private *sis_priv = netdev_priv(net_dev);
1384 struct mii_phy *phy = sis_priv->mii;
1385 int phy_addr = sis_priv->cur_phy;
1409 sis_priv->autong_complete = 1;
1418 if(netif_msg_link(sis_priv))
1437 struct sis900_private *sis_priv = netdev_priv(net_dev);
1442 if(netif_msg_tx_err(sis_priv))
1450 spin_lock_irqsave(&sis_priv->lock, flags);
1453 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1455 struct sk_buff *skb = sis_priv->tx_skbuff[i];
1458 pci_unmap_single(sis_priv->pci_dev,
1459 sis_priv->tx_ring[i].bufptr, skb->len,
1462 sis_priv->tx_skbuff[i] = NULL;
1463 sis_priv->tx_ring[i].cmdsts = 0;
1464 sis_priv->tx_ring[i].bufptr = 0;
1468 sis_priv->tx_full = 0;
1471 spin_unlock_irqrestore(&sis_priv->lock, flags);
1476 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1495 struct sis900_private *sis_priv = netdev_priv(net_dev);
1503 if(!sis_priv->autong_complete){
1508 spin_lock_irqsave(&sis_priv->lock, flags);
1511 entry = sis_priv->cur_tx % NUM_TX_DESC;
1512 sis_priv->tx_skbuff[entry] = skb;
1515 sis_priv->tx_ring[entry].bufptr = pci_map_single(sis_priv->pci_dev,
1517 sis_priv->tx_ring[entry].cmdsts = (OWN | skb->len);
1520 sis_priv->cur_tx ++;
1521 index_cur_tx = sis_priv->cur_tx;
1522 index_dirty_tx = sis_priv->dirty_tx;
1529 sis_priv->tx_full = 1;
1536 sis_priv->tx_full = 1;
1540 spin_unlock_irqrestore(&sis_priv->lock, flags);
1542 if (netif_msg_tx_queued(sis_priv))
1562 struct sis900_private *sis_priv = netdev_priv(net_dev);
1568 spin_lock (&sis_priv->lock);
1589 if(netif_msg_intr(sis_priv))
1595 if(netif_msg_intr(sis_priv))
1603 if(netif_msg_intr(sis_priv))
1608 spin_unlock (&sis_priv->lock);
1624 struct sis900_private *sis_priv = netdev_priv(net_dev);
1626 unsigned int entry = sis_priv->cur_rx % NUM_RX_DESC;
1627 u32 rx_status = sis_priv->rx_ring[entry].cmdsts;
1630 if (netif_msg_rx_status(sis_priv))
1633 sis_priv->cur_rx, sis_priv->dirty_rx, rx_status);
1634 rx_work_limit = sis_priv->dirty_rx + NUM_RX_DESC - sis_priv->cur_rx;
1654 if (netif_msg_rx_err(sis_priv))
1668 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1673 pci_unmap_single(sis_priv->pci_dev,
1674 sis_priv->rx_ring[entry].bufptr, RX_BUF_SIZE,
1686 skb = sis_priv->rx_skbuff[entry];
1694 if (sis_priv->rx_skbuff[entry] == NULL) {
1695 if (netif_msg_rx_err(sis_priv))
1699 net_dev->name, sis_priv->cur_rx,
1700 sis_priv->dirty_rx);
1705 rx_skb = sis_priv->rx_skbuff[entry];
1715 sis_priv->dirty_rx++;
1717 sis_priv->rx_skbuff[entry] = skb;
1718 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1719 sis_priv->rx_ring[entry].bufptr =
1720 pci_map_single(sis_priv->pci_dev, skb->data,
1723 sis_priv->cur_rx++;
1724 entry = sis_priv->cur_rx % NUM_RX_DESC;
1725 rx_status = sis_priv->rx_ring[entry].cmdsts;
1730 for (; sis_priv->cur_rx != sis_priv->dirty_rx; sis_priv->dirty_rx++) {
1733 entry = sis_priv->dirty_rx % NUM_RX_DESC;
1735 if (sis_priv->rx_skbuff[entry] == NULL) {
1741 if (netif_msg_rx_err(sis_priv))
1748 sis_priv->rx_skbuff[entry] = skb;
1749 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1750 sis_priv->rx_ring[entry].bufptr =
1751 pci_map_single(sis_priv->pci_dev, skb->data,
1773 struct sis900_private *sis_priv = netdev_priv(net_dev);
1775 for (; sis_priv->dirty_tx != sis_priv->cur_tx; sis_priv->dirty_tx++) {
1780 entry = sis_priv->dirty_tx % NUM_TX_DESC;
1781 tx_status = sis_priv->tx_ring[entry].cmdsts;
1792 if (netif_msg_tx_err(sis_priv))
1812 skb = sis_priv->tx_skbuff[entry];
1813 pci_unmap_single(sis_priv->pci_dev,
1814 sis_priv->tx_ring[entry].bufptr, skb->len,
1817 sis_priv->tx_skbuff[entry] = NULL;
1818 sis_priv->tx_ring[entry].bufptr = 0;
1819 sis_priv->tx_ring[entry].cmdsts = 0;
1822 if (sis_priv->tx_full && netif_queue_stopped(net_dev) &&
1823 sis_priv->cur_tx - sis_priv->dirty_tx < NUM_TX_DESC - 4) {
1826 sis_priv->tx_full = 0;
1842 struct sis900_private *sis_priv = netdev_priv(net_dev);
1855 del_timer(&sis_priv->timer);
1861 skb = sis_priv->rx_skbuff[i];
1863 pci_unmap_single(sis_priv->pci_dev,
1864 sis_priv->rx_ring[i].bufptr,
1867 sis_priv->rx_skbuff[i] = NULL;
1871 skb = sis_priv->tx_skbuff[i];
1873 pci_unmap_single(sis_priv->pci_dev,
1874 sis_priv->tx_ring[i].bufptr, skb->len,
1877 sis_priv->tx_skbuff[i] = NULL;
1897 struct sis900_private *sis_priv = netdev_priv(net_dev);
1901 strcpy (info->bus_info, pci_name(sis_priv->pci_dev));
1906 struct sis900_private *sis_priv = netdev_priv(net_dev);
1907 return sis_priv->msg_enable;
1912 struct sis900_private *sis_priv = netdev_priv(net_dev);
1913 sis_priv->msg_enable = value;
1918 struct sis900_private *sis_priv = netdev_priv(net_dev);
1919 return mii_link_ok(&sis_priv->mii_info);
1925 struct sis900_private *sis_priv = netdev_priv(net_dev);
1926 spin_lock_irq(&sis_priv->lock);
1927 mii_ethtool_gset(&sis_priv->mii_info, cmd);
1928 spin_unlock_irq(&sis_priv->lock);
1935 struct sis900_private *sis_priv = netdev_priv(net_dev);
1937 spin_lock_irq(&sis_priv->lock);
1938 rt = mii_ethtool_sset(&sis_priv->mii_info, cmd);
1939 spin_unlock_irq(&sis_priv->lock);
1945 struct sis900_private *sis_priv = netdev_priv(net_dev);
1946 return mii_nway_restart(&sis_priv->mii_info);
1962 struct sis900_private *sis_priv = netdev_priv(net_dev);
1967 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
1969 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
1971 if (netif_msg_wol(sis_priv))
1987 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
1989 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
1990 if (netif_msg_wol(sis_priv))
2033 struct sis900_private *sis_priv = netdev_priv(net_dev);
2038 data->phy_id = sis_priv->mii->phy_addr;
2065 struct sis900_private *sis_priv = netdev_priv(dev);
2066 struct mii_phy *mii_phy = sis_priv->mii;
2188 struct sis900_private *sis_priv = netdev_priv(net_dev);
2194 if((sis_priv->chipset_rev >= SIS635A_900_REV) ||
2195 (sis_priv->chipset_rev == SIS900B_900_REV))
2222 sis_priv->chipset_rev);
2262 struct sis900_private *sis_priv = netdev_priv(net_dev);
2278 if( (sis_priv->chipset_rev >= SIS635A_900_REV) ||
2279 (sis_priv->chipset_rev == SIS900B_900_REV) )
2295 struct sis900_private *sis_priv = netdev_priv(net_dev);
2298 while (sis_priv->first_mii) {
2299 phy = sis_priv->first_mii;
2300 sis_priv->first_mii = phy->next;
2304 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
2305 sis_priv->rx_ring_dma);
2306 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
2307 sis_priv->tx_ring_dma);
2339 struct sis900_private *sis_priv = netdev_priv(net_dev);
2364 sis900_check_mode(net_dev, sis_priv->mii);