Lines Matching refs:read_ir_reg
76 u32 read_ir_reg(u32 addr)
323 writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); /* disable PHY */
371 writel(read_ir_reg(IR_CONFIG_2) | 1<<8, IR_CONFIG_2); /* int enable */
383 writel(read_ir_reg(IR_CONFIG_2) & ~(1<<8), IR_CONFIG_2);
462 writel(read_ir_reg(IR_CONFIG_1) & ~IR_TX_ENABLE,
465 writel(read_ir_reg(IR_CONFIG_1) | IR_RX_ENABLE,
537 writel(read_ir_reg(IR_CONFIG_1) | IR_TX_ENABLE, IR_CONFIG_1);
672 writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE);
675 writel(read_ir_reg(IR_CONFIG_1) & ~(IR_RX_ENABLE|IR_TX_ENABLE),
678 while (read_ir_reg(IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) {
688 writel(read_ir_reg(IR_CONFIG_1) & ~IR_DMA_ENABLE, IR_CONFIG_1);
757 writel(read_ir_reg(IR_ENABLE) | 0x8000, IR_ENABLE);
760 control = read_ir_reg(IR_ENABLE);