Lines Matching refs:hw
215 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
216 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
217 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
218 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
219 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
221 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
223 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
225 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
227 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
228 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
229 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
230 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
231 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
232 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
233 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
234 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
235 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
236 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
237 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
238 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
239 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
240 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
241 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
242 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
243 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
244 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
245 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
246 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
248 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
250 return readw(hw->flash_address + reg);
253 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
255 return readl(hw->flash_address + reg);
258 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
260 writew(val, hw->flash_address + reg);
263 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
265 writel(val, hw->flash_address + reg);
268 #define er16flash(reg) __er16flash(hw, (reg))
269 #define er32flash(reg) __er32flash(hw, (reg))
270 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
271 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
275 * @hw: pointer to the HW structure
279 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
281 struct e1000_phy_info *phy = &hw->phy;
319 if (hw->mac.type == e1000_pch2lan)
320 e1000_gate_hw_phy_config_ich8lan(hw, true);
329 ret_val = e1000e_phy_hw_reset_generic(hw);
334 if ((hw->mac.type == e1000_pch2lan) &&
337 e1000_gate_hw_phy_config_ich8lan(hw, false);
341 ret_val = e1000e_get_phy_id(hw);
349 ret_val = e1000_set_mdio_slow_mode_hv(hw);
352 ret_val = e1000e_get_phy_id(hw);
385 * @hw: pointer to the HW structure
389 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
391 struct e1000_phy_info *phy = &hw->phy;
405 ret_val = e1000e_determine_phy_address(hw);
409 ret_val = e1000e_determine_phy_address(hw);
420 ret_val = e1000e_get_phy_id(hw);
465 * @hw: pointer to the HW structure
470 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
472 struct e1000_nvm_info *nvm = &hw->nvm;
473 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
478 if (!hw->flash_address) {
521 * @hw: pointer to the HW structure
528 struct e1000_hw *hw = &adapter->hw;
529 struct e1000_mac_info *mac = &hw->mac;
532 hw->phy.media_type = e1000_media_type_copper;
583 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
588 e1000_gate_hw_phy_config_ich8lan(hw, true);
595 * @hw: pointer to the HW structure
600 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
605 if (hw->phy.type != e1000_phy_82579)
608 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
612 if (hw->dev_spec.ich8lan.eee_disable)
617 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
624 * @hw: pointer to the HW structure
630 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
632 struct e1000_mac_info *mac = &hw->mac;
652 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
656 if (hw->mac.type == e1000_pchlan) {
657 ret_val = e1000_k1_gig_workaround_hv(hw, link);
667 if (hw->phy.type == e1000_phy_82578) {
668 ret_val = e1000_link_stall_workaround_hv(hw);
673 if (hw->mac.type == e1000_pch2lan) {
674 ret_val = e1000_k1_workaround_lv(hw);
683 e1000e_check_downshift(hw);
686 ret_val = e1000_set_eee_pchlan(hw);
704 e1000e_config_collision_dist(hw);
712 ret_val = e1000e_config_fc_after_link_up(hw);
722 struct e1000_hw *hw = &adapter->hw;
729 rc = e1000_init_nvm_params_ich8lan(hw);
733 switch (hw->mac.type) {
737 rc = e1000_init_phy_params_ich8lan(hw);
741 rc = e1000_init_phy_params_pchlan(hw);
749 if (adapter->hw.phy.type == e1000_phy_ife) {
754 if ((adapter->hw.mac.type == e1000_ich8lan) &&
755 (adapter->hw.phy.type == e1000_phy_igp_3))
760 adapter->hw.dev_spec.ich8lan.eee_disable = true;
769 * @hw: pointer to the HW structure
773 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
782 * @hw: pointer to the HW structure
786 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
795 * @hw: pointer to the HW structure
800 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
853 * @hw: pointer to the HW structure
858 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
871 * @hw: pointer to the HW structure
877 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
889 * @hw: pointer to the HW structure
895 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
906 * @hw: pointer to the HW structure
912 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
923 * @hw: pointer to the HW structure
928 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
936 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
943 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
949 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
951 struct e1000_phy_info *phy = &hw->phy;
963 switch (hw->mac.type) {
968 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
969 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
982 ret_val = hw->phy.ops.acquire(hw);
995 if (!(hw->mac.type == e1000_pch2lan)) {
1010 (hw->mac.type == e1000_pchlan)) ||
1011 (hw->mac.type == e1000_pch2lan)) {
1018 ret_val = e1000_write_smbus_addr(hw);
1023 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1035 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1040 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1054 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1061 hw->phy.ops.release(hw);
1065 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1069 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1071 if (hw->mac.type != e1000_pchlan)
1075 ret_val = hw->phy.ops.acquire(hw);
1081 if (hw->phy.type == e1000_phy_82578) {
1082 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1097 if (hw->phy.type == e1000_phy_82577) {
1098 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1114 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1121 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1127 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1130 hw->phy.ops.release(hw);
1137 * @hw: pointer to the HW structure
1145 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1153 ret_val = e1000e_read_kmrn_reg_locked(hw,
1164 ret_val = e1000e_write_kmrn_reg_locked(hw,
1190 * @hw: pointer to the HW structure
1197 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1203 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1206 ret_val = hw->phy.ops.acquire(hw);
1210 if (!(hw->mac.type == e1000_pch2lan)) {
1222 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1242 if (!e1000_check_reset_block(hw))
1244 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1247 hw->phy.ops.release(hw);
1255 * @hw: pointer to the HW structure
1257 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1262 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1268 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1277 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1282 if (hw->mac.type != e1000_pchlan)
1286 if (hw->phy.type == e1000_phy_82577) {
1287 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1292 if (((hw->phy.type == e1000_phy_82577) &&
1293 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1294 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1296 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1301 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1306 if (hw->phy.type == e1000_phy_82578) {
1311 if (hw->phy.revision < 2) {
1312 e1000e_phy_sw_reset(hw);
1313 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1318 ret_val = hw->phy.ops.acquire(hw);
1322 hw->phy.addr = 1;
1323 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1324 hw->phy.ops.release(hw);
1328 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1332 ret_val = hw->phy.ops.acquire(hw);
1335 ret_val = hw->phy.ops.read_reg_locked(hw,
1340 ret_val = hw->phy.ops.write_reg_locked(hw,
1344 hw->phy.ops.release(hw);
1351 * @hw: pointer to the HW structure
1353 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1359 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1361 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1362 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1364 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1365 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1385 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1392 if (hw->mac.type != e1000_pch2lan)
1395 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1396 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1405 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1425 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1436 ret_val = e1000e_read_kmrn_reg(hw,
1441 ret_val = e1000e_write_kmrn_reg(hw,
1446 ret_val = e1000e_read_kmrn_reg(hw,
1453 ret_val = e1000e_write_kmrn_reg(hw,
1459 e1e_rphy(hw, PHY_REG(769, 23), &data);
1462 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1465 e1e_rphy(hw, PHY_REG(769, 16), &data);
1467 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1470 e1e_rphy(hw, PHY_REG(776, 20), &data);
1473 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1476 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1479 e1e_rphy(hw, HV_PM_CTRL, &data);
1480 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1493 ret_val = e1000e_read_kmrn_reg(hw,
1498 ret_val = e1000e_write_kmrn_reg(hw,
1503 ret_val = e1000e_read_kmrn_reg(hw,
1510 ret_val = e1000e_write_kmrn_reg(hw,
1517 e1e_rphy(hw, PHY_REG(769, 23), &data);
1519 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1522 e1e_rphy(hw, PHY_REG(769, 16), &data);
1524 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1527 e1e_rphy(hw, PHY_REG(776, 20), &data);
1530 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1533 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1536 e1e_rphy(hw, HV_PM_CTRL, &data);
1537 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1542 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1552 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1556 if (hw->mac.type != e1000_pch2lan)
1560 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1566 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1572 if (hw->mac.type != e1000_pch2lan)
1576 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1599 * @hw: pointer to the HW structure
1605 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1609 if (hw->mac.type != e1000_pch2lan)
1625 * @hw: pointer to the HW structure
1630 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1657 * @hw: pointer to the HW structure
1659 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1664 if (e1000_check_reset_block(hw))
1671 switch (hw->mac.type) {
1673 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1678 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1687 if (hw->mac.type >= e1000_pchlan)
1688 e1e_rphy(hw, BM_WUC, ®);
1691 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1696 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1699 if ((hw->mac.type == e1000_pch2lan) &&
1702 e1000_gate_hw_phy_config_ich8lan(hw, false);
1711 * @hw: pointer to the HW structure
1717 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1722 if ((hw->mac.type == e1000_pch2lan) &&
1724 e1000_gate_hw_phy_config_ich8lan(hw, true);
1726 ret_val = e1000e_phy_hw_reset_generic(hw);
1730 ret_val = e1000_post_phy_reset_ich8lan(hw);
1738 * @hw: pointer to the HW structure
1744 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1747 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1752 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1762 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1770 * @hw: pointer to the HW structure
1781 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1783 struct e1000_phy_info *phy = &hw->phy;
1800 if (hw->mac.type == e1000_ich8lan)
1801 e1000e_gig_downshift_workaround_ich8lan(hw);
1804 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1806 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1823 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1829 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1834 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1840 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1852 * @hw: pointer to the HW structure
1863 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1865 struct e1000_phy_info *phy = &hw->phy;
1886 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1892 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1897 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1903 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1917 if (hw->mac.type == e1000_ich8lan)
1918 e1000e_gig_downshift_workaround_ich8lan(hw);
1921 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1926 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1934 * @hw: pointer to the HW structure
1940 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1943 struct e1000_nvm_info *nvm = &hw->nvm;
1949 switch (hw->mac.type) {
1970 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1981 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2001 * @hw: pointer to the HW structure
2008 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2011 struct e1000_nvm_info *nvm = &hw->nvm;
2012 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2025 nvm->ops.acquire(hw);
2027 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2042 ret_val = e1000_read_flash_word_ich8lan(hw,
2051 nvm->ops.release(hw);
2062 * @hw: pointer to the HW structure
2067 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2082 /* Clear FCERR and DAEL in hw status by writing 1 */
2112 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2136 * @hw: pointer to the HW structure
2141 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2169 * @hw: pointer to the HW structure
2176 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2182 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2187 * @hw: pointer to the HW structure
2193 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2199 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2210 * @hw: pointer to the HW structure
2217 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2231 hw->nvm.flash_base_addr;
2236 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2248 ret_val = e1000_flash_cycle_ich8lan(hw,
2289 * @hw: pointer to the HW structure
2296 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2299 struct e1000_nvm_info *nvm = &hw->nvm;
2300 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2309 nvm->ops.acquire(hw);
2316 nvm->ops.release(hw);
2323 * @hw: pointer to the HW structure
2332 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2334 struct e1000_nvm_info *nvm = &hw->nvm;
2335 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2340 ret_val = e1000e_update_nvm_checksum_generic(hw);
2347 nvm->ops.acquire(hw);
2354 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2363 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2369 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2383 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2406 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2413 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2437 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2442 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2455 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2466 nvm->ops.release(hw);
2473 e1000e_reload_nvm(hw);
2486 * @hw: pointer to the HW structure
2492 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2503 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2509 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2512 ret_val = e1000e_update_nvm_checksum(hw);
2517 return e1000e_validate_nvm_checksum_generic(hw);
2522 * @hw: pointer to the HW structure
2530 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2532 struct e1000_nvm_info *nvm = &hw->nvm;
2537 nvm->ops.acquire(hw);
2552 nvm->ops.release(hw);
2557 * @hw: pointer to the HW structure
2564 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2579 hw->nvm.flash_base_addr;
2584 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2607 ret_val = e1000_flash_cycle_ich8lan(hw,
2634 * @hw: pointer to the HW structure
2640 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2645 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2650 * @hw: pointer to the HW structure
2657 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2663 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2670 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2682 * @hw: pointer to the HW structure
2688 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2690 struct e1000_nvm_info *nvm = &hw->nvm;
2703 * Determine HW Sector size: Read BERASE bits of hw flash status
2738 flash_linear_addr = hw->nvm.flash_base_addr;
2744 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2750 * Cycle field in hw flash control
2764 ret_val = e1000_flash_cycle_ich8lan(hw,
2788 * @hw: pointer to the HW structure
2795 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2799 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2814 * @hw: pointer to the HW structure
2825 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2827 struct e1000_mac_info *mac = &hw->mac;
2834 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2887 * @hw: pointer to the HW structure
2892 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2894 struct e1000_bus_info *bus = &hw->bus;
2897 ret_val = e1000e_get_bus_info_pcie(hw);
2913 * @hw: pointer to the HW structure
2918 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2920 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2929 ret_val = e1000e_disable_pcie_master(hw);
2947 if (hw->mac.type == e1000_ich8lan) {
2954 if (hw->mac.type == e1000_pchlan) {
2956 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
2968 if (!e1000_check_reset_block(hw)) {
2980 if ((hw->mac.type == e1000_pch2lan) &&
2982 e1000_gate_hw_phy_config_ich8lan(hw, true);
2984 ret_val = e1000_acquire_swflag_ich8lan(hw);
2990 e1000_release_swflag_ich8lan(hw);
2993 ret_val = hw->phy.ops.get_cfg_done(hw);
2997 ret_val = e1000_post_phy_reset_ich8lan(hw);
3007 if (hw->mac.type == e1000_pchlan)
3023 * @hw: pointer to the HW structure
3033 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3035 struct e1000_mac_info *mac = &hw->mac;
3040 e1000_initialize_hw_bits_ich8lan(hw);
3043 ret_val = mac->ops.id_led_init(hw);
3049 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3054 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3061 if (hw->phy.type == e1000_phy_82578) {
3062 hw->phy.ops.read_reg(hw, BM_WUC, &i);
3063 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3069 ret_val = e1000_setup_link_ich8lan(hw);
3093 e1000e_set_pcie_no_snoop(hw, snoop);
3105 e1000_clear_hw_cntrs_ich8lan(hw);
3111 * @hw: pointer to the HW structure
3116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3124 if (hw->mac.type >= e1000_pchlan)
3140 if (hw->mac.type == e1000_ich8lan)
3155 if (hw->mac.type == e1000_ich8lan) {
3168 * @hw: pointer to the HW structure
3176 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3180 if (e1000_check_reset_block(hw))
3188 if (hw->fc.requested_mode == e1000_fc_default) {
3189 if (hw->mac.type == e1000_pchlan)
3190 hw->fc.requested_mode = e1000_fc_rx_pause;
3192 hw->fc.requested_mode = e1000_fc_full;
3199 hw->fc.current_mode = hw->fc.requested_mode;
3202 hw->fc.current_mode);
3205 ret_val = e1000_setup_copper_link_ich8lan(hw);
3209 ew32(FCTTV, hw->fc.pause_time);
3210 if ((hw->phy.type == e1000_phy_82578) ||
3211 (hw->phy.type == e1000_phy_82579) ||
3212 (hw->phy.type == e1000_phy_82577)) {
3213 ew32(FCRTV_PCH, hw->fc.refresh_time);
3215 ret_val = hw->phy.ops.write_reg(hw,
3217 hw->fc.pause_time);
3222 return e1000e_set_fc_watermarks(hw);
3227 * @hw: pointer to the HW structure
3233 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3249 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3252 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3257 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3262 switch (hw->phy.type) {
3264 ret_val = e1000e_copper_link_setup_igp(hw);
3270 ret_val = e1000e_copper_link_setup_m88(hw);
3276 ret_val = e1000_copper_link_setup_82577(hw);
3281 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3288 switch (hw->phy.mdix) {
3300 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3308 return e1000e_setup_copper_link(hw);
3311 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3316 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3320 if ((hw->mac.type == e1000_ich8lan) &&
3321 (hw->phy.type == e1000_phy_igp_3) &&
3323 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3329 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3331 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3345 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3351 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3355 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3364 e1000_phy_hw_reset(hw);
3373 e1000e_gig_downshift_workaround_ich8lan(hw);
3379 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3382 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3384 if (hw->mac.type != e1000_ich8lan) {
3392 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3398 if (hw->phy.type != e1000_phy_igp_3)
3408 if (hw->mac.type == e1000_ich8lan)
3409 e1000e_gig_downshift_workaround_ich8lan(hw);
3412 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3414 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3417 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3431 * @hw: pointer to the HW structure
3439 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3444 if ((hw->mac.type != e1000_ich8lan) ||
3445 (hw->phy.type != e1000_phy_igp_3))
3448 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3453 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3458 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3464 * @hw: pointer to the HW structure
3473 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3482 if (hw->mac.type >= e1000_pchlan) {
3483 e1000_oem_bits_config_ich8lan(hw, true);
3484 ret_val = hw->phy.ops.acquire(hw);
3487 e1000_write_smbus_addr(hw);
3488 hw->phy.ops.release(hw);
3494 * @hw: pointer to the HW structure
3498 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3500 if (hw->phy.type == e1000_phy_ife)
3501 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3503 ew32(LEDCTL, hw->mac.ledctl_default);
3509 * @hw: pointer to the HW structure
3513 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3515 if (hw->phy.type == e1000_phy_ife)
3516 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3519 ew32(LEDCTL, hw->mac.ledctl_mode2);
3525 * @hw: pointer to the HW structure
3529 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3531 if (hw->phy.type == e1000_phy_ife)
3532 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3535 ew32(LEDCTL, hw->mac.ledctl_mode1);
3541 * @hw: pointer to the HW structure
3545 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3547 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3548 (u16)hw->mac.ledctl_mode1);
3553 * @hw: pointer to the HW structure
3557 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3559 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3560 (u16)hw->mac.ledctl_default);
3565 * @hw: pointer to the HW structure
3569 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3571 u16 data = (u16)hw->mac.ledctl_mode2;
3591 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3596 * @hw: pointer to the HW structure
3600 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3602 u16 data = (u16)hw->mac.ledctl_mode1;
3622 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3627 * @hw: pointer to the HW structure
3637 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3643 e1000e_get_cfg_done(hw);
3646 if (hw->mac.type >= e1000_ich10lan) {
3647 e1000_lan_init_done_ich8lan(hw);
3649 ret_val = e1000e_get_auto_rd_done(hw);
3669 if (hw->mac.type <= e1000_ich9lan) {
3671 (hw->phy.type == e1000_phy_igp_3)) {
3672 e1000e_phy_init_script_igp3(hw);
3675 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3687 * @hw: pointer to the HW structure
3692 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3695 if (!(hw->mac.ops.check_mng_mode(hw) ||
3696 hw->phy.ops.check_reset_block(hw)))
3697 e1000_power_down_phy_copper(hw);
3702 * @hw: pointer to the HW structure
3707 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3711 e1000e_clear_hw_cntrs_base(hw);
3728 if ((hw->phy.type == e1000_phy_82578) ||
3729 (hw->phy.type == e1000_phy_82579) ||
3730 (hw->phy.type == e1000_phy_82577)) {
3731 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3732 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3733 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3734 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3735 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3736 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3737 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3738 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3739 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3740 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3741 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3742 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3743 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3744 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);