Lines Matching defs:ret_val
283 s32 ret_val = 0;
329 ret_val = e1000e_phy_hw_reset_generic(hw);
330 if (ret_val)
341 ret_val = e1000e_get_phy_id(hw);
342 if (ret_val)
349 ret_val = e1000_set_mdio_slow_mode_hv(hw);
350 if (ret_val)
352 ret_val = e1000e_get_phy_id(hw);
353 if (ret_val)
375 ret_val = -E1000_ERR_PHY;
380 return ret_val;
392 s32 ret_val;
405 ret_val = e1000e_determine_phy_address(hw);
406 if (ret_val) {
409 ret_val = e1000e_determine_phy_address(hw);
410 if (ret_val) {
412 return ret_val;
420 ret_val = e1000e_get_phy_id(hw);
421 if (ret_val)
422 return ret_val;
602 s32 ret_val = 0;
608 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
609 if (ret_val)
617 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
619 return ret_val;
633 s32 ret_val;
643 ret_val = 0;
652 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
653 if (ret_val)
657 ret_val = e1000_k1_gig_workaround_hv(hw, link);
658 if (ret_val)
668 ret_val = e1000_link_stall_workaround_hv(hw);
669 if (ret_val)
674 ret_val = e1000_k1_workaround_lv(hw);
675 if (ret_val)
686 ret_val = e1000_set_eee_pchlan(hw);
687 if (ret_val)
695 ret_val = -E1000_ERR_CONFIG;
712 ret_val = e1000e_config_fc_after_link_up(hw);
713 if (ret_val)
717 return ret_val;
803 s32 ret_val = 0;
818 ret_val = -E1000_ERR_CONFIG;
840 ret_val = -E1000_ERR_CONFIG;
845 if (ret_val)
848 return ret_val;
932 s32 ret_val = 0;
936 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
937 if (ret_val)
943 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
946 return ret_val;
953 s32 ret_val = 0;
966 return ret_val;
979 return ret_val;
982 ret_val = hw->phy.ops.acquire(hw);
983 if (ret_val)
984 return ret_val;
1018 ret_val = e1000_write_smbus_addr(hw);
1019 if (ret_val)
1023 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1025 if (ret_val)
1035 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1037 if (ret_val)
1040 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1042 if (ret_val)
1054 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1056 if (ret_val)
1062 return ret_val;
1067 s32 ret_val = 0;
1075 ret_val = hw->phy.ops.acquire(hw);
1076 if (ret_val)
1082 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1084 if (ret_val)
1098 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1100 if (ret_val)
1114 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1116 if (ret_val)
1121 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1123 if (ret_val)
1127 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1132 return ret_val;
1147 s32 ret_val = 0;
1153 ret_val = e1000e_read_kmrn_reg_locked(hw,
1156 if (ret_val)
1164 ret_val = e1000e_write_kmrn_reg_locked(hw,
1167 if (ret_val)
1185 return ret_val;
1199 s32 ret_val = 0;
1204 return ret_val;
1206 ret_val = hw->phy.ops.acquire(hw);
1207 if (ret_val)
1208 return ret_val;
1222 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1223 if (ret_val)
1244 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1249 return ret_val;
1259 s32 ret_val;
1262 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1263 if (ret_val)
1264 return ret_val;
1268 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1270 return ret_val;
1279 s32 ret_val = 0;
1283 return ret_val;
1287 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1288 if (ret_val)
1296 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1297 if (ret_val)
1298 return ret_val;
1301 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1302 if (ret_val)
1303 return ret_val;
1313 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1318 ret_val = hw->phy.ops.acquire(hw);
1319 if (ret_val)
1320 return ret_val;
1323 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1325 if (ret_val)
1328 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1329 if (ret_val)
1332 ret_val = hw->phy.ops.acquire(hw);
1333 if (ret_val)
1335 ret_val = hw->phy.ops.read_reg_locked(hw,
1338 if (ret_val)
1340 ret_val = hw->phy.ops.write_reg_locked(hw,
1346 return ret_val;
1387 s32 ret_val = 0;
1396 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1397 if (ret_val)
1436 ret_val = e1000e_read_kmrn_reg(hw,
1439 if (ret_val)
1441 ret_val = e1000e_write_kmrn_reg(hw,
1444 if (ret_val)
1446 ret_val = e1000e_read_kmrn_reg(hw,
1449 if (ret_val)
1453 ret_val = e1000e_write_kmrn_reg(hw,
1456 if (ret_val)
1462 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1463 if (ret_val)
1467 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1468 if (ret_val)
1473 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1474 if (ret_val)
1476 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1477 if (ret_val)
1480 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1481 if (ret_val)
1493 ret_val = e1000e_read_kmrn_reg(hw,
1496 if (ret_val)
1498 ret_val = e1000e_write_kmrn_reg(hw,
1501 if (ret_val)
1503 ret_val = e1000e_read_kmrn_reg(hw,
1506 if (ret_val)
1510 ret_val = e1000e_write_kmrn_reg(hw,
1513 if (ret_val)
1519 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1520 if (ret_val)
1524 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1525 if (ret_val)
1530 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1531 if (ret_val)
1533 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1534 if (ret_val)
1537 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1538 if (ret_val)
1542 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1545 return ret_val;
1554 s32 ret_val = 0;
1560 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1563 return ret_val;
1568 s32 ret_val = 0;
1576 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1577 if (ret_val)
1594 return ret_val;
1661 s32 ret_val = 0;
1673 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1674 if (ret_val)
1678 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1679 if (ret_val)
1691 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1692 if (ret_val)
1696 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1706 return ret_val;
1719 s32 ret_val = 0;
1726 ret_val = e1000e_phy_hw_reset_generic(hw);
1727 if (ret_val)
1730 ret_val = e1000_post_phy_reset_ich8lan(hw);
1733 return ret_val;
1749 s32 ret_val = 0;
1752 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1753 if (ret_val)
1762 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1765 return ret_val;
1785 s32 ret_val = 0;
1789 return ret_val;
1804 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1806 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1807 if (ret_val)
1808 return ret_val;
1823 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1825 if (ret_val)
1826 return ret_val;
1829 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1831 if (ret_val)
1832 return ret_val;
1834 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1836 if (ret_val)
1837 return ret_val;
1840 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1842 if (ret_val)
1843 return ret_val;
1867 s32 ret_val;
1886 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1888 if (ret_val)
1889 return ret_val;
1892 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1894 if (ret_val)
1895 return ret_val;
1897 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1899 if (ret_val)
1900 return ret_val;
1903 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1905 if (ret_val)
1906 return ret_val;
1921 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1922 if (ret_val)
1923 return ret_val;
1926 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1947 s32 ret_val = 0;
1970 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1972 if (ret_val)
1973 return ret_val;
1981 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1984 if (ret_val)
1985 return ret_val;
2014 s32 ret_val = 0;
2021 ret_val = -E1000_ERR_NVM;
2027 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2028 if (ret_val) {
2036 ret_val = 0;
2042 ret_val = e1000_read_flash_word_ich8lan(hw,
2045 if (ret_val)
2054 if (ret_val)
2055 e_dbg("NVM read error: %d\n", ret_val);
2057 return ret_val;
2070 s32 ret_val = -E1000_ERR_NVM;
2105 ret_val = 0;
2114 ret_val = 0;
2119 if (ret_val == 0) {
2131 return ret_val;
2145 s32 ret_val = -E1000_ERR_NVM;
2164 return ret_val;
2196 s32 ret_val;
2199 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2200 if (ret_val)
2201 return ret_val;
2224 s32 ret_val = -E1000_ERR_NVM;
2236 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2237 if (ret_val != 0)
2248 ret_val = e1000_flash_cycle_ich8lan(hw,
2257 if (ret_val == 0) {
2284 return ret_val;
2337 s32 ret_val;
2340 ret_val = e1000e_update_nvm_checksum_generic(hw);
2341 if (ret_val)
2354 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2355 if (ret_val) {
2363 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2364 if (ret_val)
2369 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2370 if (ret_val)
2383 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2386 if (ret_val)
2406 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2409 if (ret_val)
2413 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2416 if (ret_val)
2424 if (ret_val) {
2437 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2438 if (ret_val)
2442 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2445 if (ret_val)
2455 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2456 if (ret_val)
2472 if (!ret_val) {
2478 if (ret_val)
2479 e_dbg("NVM update error: %d\n", ret_val);
2481 return ret_val;
2494 s32 ret_val;
2503 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2504 if (ret_val)
2505 return ret_val;
2509 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2510 if (ret_val)
2511 return ret_val;
2512 ret_val = e1000e_update_nvm_checksum(hw);
2513 if (ret_val)
2514 return ret_val;
2571 s32 ret_val;
2584 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2585 if (ret_val)
2607 ret_val = e1000_flash_cycle_ich8lan(hw,
2609 if (!ret_val)
2629 return ret_val;
2660 s32 ret_val;
2663 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2664 if (!ret_val)
2665 return ret_val;
2670 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2671 if (!ret_val)
2696 s32 ret_val;
2744 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2745 if (ret_val)
2746 return ret_val;
2764 ret_val = e1000_flash_cycle_ich8lan(hw,
2766 if (ret_val == 0)
2779 return ret_val;
2797 s32 ret_val;
2799 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2800 if (ret_val) {
2802 return ret_val;
2828 s32 ret_val;
2834 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2835 if (ret_val)
2882 return ret_val;
2895 s32 ret_val;
2897 ret_val = e1000e_get_bus_info_pcie(hw);
2908 return ret_val;
2923 s32 ret_val;
2929 ret_val = e1000e_disable_pcie_master(hw);
2930 if (ret_val)
2956 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
2957 if (ret_val)
2958 return ret_val;
2984 ret_val = e1000_acquire_swflag_ich8lan(hw);
2989 if (!ret_val)
2993 ret_val = hw->phy.ops.get_cfg_done(hw);
2994 if (ret_val)
2997 ret_val = e1000_post_phy_reset_ich8lan(hw);
2998 if (ret_val)
3018 return ret_val;
3037 s32 ret_val;
3043 ret_val = mac->ops.id_led_init(hw);
3044 if (ret_val)
3063 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3064 if (ret_val)
3065 return ret_val;
3069 ret_val = e1000_setup_link_ich8lan(hw);
3178 s32 ret_val;
3205 ret_val = e1000_setup_copper_link_ich8lan(hw);
3206 if (ret_val)
3207 return ret_val;
3215 ret_val = hw->phy.ops.write_reg(hw,
3218 if (ret_val)
3219 return ret_val;
3236 s32 ret_val;
3249 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3250 if (ret_val)
3251 return ret_val;
3252 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3254 if (ret_val)
3255 return ret_val;
3257 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3259 if (ret_val)
3260 return ret_val;
3264 ret_val = e1000e_copper_link_setup_igp(hw);
3265 if (ret_val)
3266 return ret_val;
3270 ret_val = e1000e_copper_link_setup_m88(hw);
3271 if (ret_val)
3272 return ret_val;
3276 ret_val = e1000_copper_link_setup_82577(hw);
3277 if (ret_val)
3278 return ret_val;
3281 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3283 if (ret_val)
3284 return ret_val;
3300 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3302 if (ret_val)
3303 return ret_val;
3314 s32 ret_val;
3316 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3317 if (ret_val)
3318 return ret_val;
3323 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3326 return ret_val;
3333 s32 ret_val;
3345 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3351 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3352 if (ret_val)
3353 return ret_val;
3355 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3356 if (ret_val)
3357 return ret_val;
3441 s32 ret_val;
3448 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3450 if (ret_val)
3453 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3455 if (ret_val)
3458 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3476 s32 ret_val;
3484 ret_val = hw->phy.ops.acquire(hw);
3485 if (ret_val)
3639 s32 ret_val = 0;
3649 ret_val = e1000e_get_auto_rd_done(hw);
3650 if (ret_val) {
3657 ret_val = 0;
3678 ret_val = -E1000_ERR_CONFIG;
3682 return ret_val;