Lines Matching refs:divider
179 * Note the largest clock divider value of 0xffff corresponds to:
200 static inline unsigned int clock_divider_to_ns(unsigned int divider)
203 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
213 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
215 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
225 static inline unsigned int clock_divider_to_freq(unsigned int divider,
229 (divider + 1) * rollovers);
270 static u32 clock_divider_to_resolution(u16 divider)
277 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
281 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
290 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
297 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
306 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
317 * significant part and (up to) 16 bit clock divider count as a modulus.
318 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
451 u16 *divider)
453 *divider = carrier_freq_to_clock_divider(freq);
454 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
455 return clock_divider_to_carrier_freq(*divider);
460 u16 *divider)
462 *divider = carrier_freq_to_clock_divider(freq);
463 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
464 return clock_divider_to_carrier_freq(*divider);
468 u16 *divider)
475 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
476 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
477 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
481 u16 *divider)
488 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
489 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
490 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
672 u16 divider = (u16) atomic_read(&state->rxclk_divider);
703 (u16) (p->hw_fifo_data & FIFO_RXTX), divider);