Lines Matching refs:saa7146_write
24 saa7146_write(dev, BASE_EVEN3, dma_addr);
25 saa7146_write(dev, BASE_ODD3, dma_addr+vbi_pixel_to_capture);
26 saa7146_write(dev, PROT_ADDR3, dma_addr+4096);
27 saa7146_write(dev, PITCH3, vbi_pixel_to_capture);
28 saa7146_write(dev, BASE_PAGE3, 0x0);
29 saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0));
30 saa7146_write(dev, MC2, MASK_04|MASK_20);
80 saa7146_write(dev, MC2, MASK_31|MASK_15);
82 saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0));
83 saa7146_write(dev, MC2, MASK_04|MASK_20);
92 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
93 saa7146_write(dev, MC1, (MASK_13 | MASK_29));
106 saa7146_write(dev, MC1, MASK_20);
113 saa7146_write(dev, MC1, MASK_29);
188 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
191 saa7146_write(dev, MC1, (MASK_13 | MASK_29));
320 saa7146_write(dev, MC1, MASK_29);
326 saa7146_write(dev, MC1, MASK_20);
385 saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
386 saa7146_write(dev, MC2, (MASK_04|MASK_20));
413 saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));
415 saa7146_write(dev, BRS_CTRL, 0x00000001);
424 saa7146_write(dev, MC2, (MASK_08|MASK_24));