Lines Matching defs:ireg
90 rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg)
95 if (msg && ireg->clsb) {
97 for (i=1; i < ireg->clsb; i++)
103 i = ireg->clsb;
106 t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
107 QuickHex(t, &msg[ireg->clsb-i], (i>64) ? 64:i);
119 get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
121 ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS);
122 ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H);
123 ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L);
126 debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
127 ireg->clsb);
198 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
265 if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
267 ireg->iis, ireg->cmsb, len);
315 if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
317 ireg->iis, ireg->cmsb, len);
331 ireg->bstat = 0;
341 if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
343 ireg->iis, ireg->cmsb, len);
352 while ((!ireg->bstat) && cnt) {
361 ireg->bstat);
368 ireg->iis = 0;
375 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
384 if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
385 && (ireg->par[0] == 0)) {
389 ireg->cmsb, ireg->clsb, ireg->par[0]);
393 ireg->iis = 0;
400 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
409 if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
411 ireg->par[0]);
414 ireg->cmsb, ireg->clsb, cnt);
494 struct isar_reg *ireg = bcs->hw.isar.reg;
496 if (!ireg->clsb) {
504 ireg->iis, ireg->cmsb, ireg->clsb);
506 ireg->iis, ireg->cmsb, ireg->clsb);
511 if ((skb = dev_alloc_skb(ireg->clsb))) {
512 rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb));
521 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
526 } else if (ireg->cmsb & HDLC_ERROR) {
529 ireg->cmsb, ireg->clsb);
531 if (ireg->cmsb & HDLC_ERR_RER)
533 if (ireg->cmsb & HDLC_ERR_CER)
539 if (ireg->cmsb & HDLC_FSD)
542 bcs->hw.isar.rcvidx += ireg->clsb;
543 rcv_mbox(cs, ireg, ptr);
544 if (ireg->cmsb & HDLC_FED) {
570 rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf);
571 bcs->hw.isar.rcvidx = ireg->clsb +
572 dle_count(bcs->hw.isar.rcvbuf, ireg->clsb);
575 ireg->clsb, bcs->hw.isar.rcvidx);
578 bcs->hw.isar.rcvbuf, ireg->clsb);
581 if (ireg->cmsb & SART_NMD) { /* ABORT */
606 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
611 } else if (ireg->cmsb & HDLC_ERROR) {
614 ireg->cmsb, ireg->clsb);
618 if (ireg->cmsb & HDLC_FSD) {
622 bcs->hw.isar.rcvidx += ireg->clsb;
623 rcv_mbox(cs, ireg, ptr);
624 if (ireg->cmsb & HDLC_FED) {
648 if (ireg->cmsb & SART_NMD) { /* ABORT */
842 isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
844 u_char ril = ireg->par[0];
854 switch(ireg->par[1]) {
1175 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
1178 get_irq_infos(cs, ireg);
1179 switch (ireg->iis & ISAR_IIS_MSCMSD) {
1181 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1185 ireg->iis, ireg->cmsb, ireg->clsb);
1191 ireg->bstat |= ireg->cmsb;
1192 check_send(cs, ireg->cmsb);
1196 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1197 if (ireg->cmsb == BSTEV_TBO)
1199 if (ireg->cmsb == BSTEV_RBO)
1205 ireg->iis>>6, ireg->cmsb);
1209 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1210 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1212 isar_pump_statev_modem(bcs, ireg->cmsb);
1214 isar_pump_statev_fax(bcs, ireg->cmsb);
1215 } else if (ireg->cmsb == PSEV_10MS_TIMER) {
1221 bcs->mode, ireg->cmsb);
1225 ireg->iis, ireg->cmsb, ireg->clsb);
1230 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1231 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1232 isar_pump_status_rsp(bcs, ireg);
1235 ireg->iis, ireg->cmsb, ireg->clsb);
1242 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1248 ireg->iis, ireg->cmsb);
1249 QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
1254 rcv_mbox(cs, ireg, debbuf);
1257 ireg->cmsb);
1260 rcv_mbox(cs, ireg, debbuf);
1263 ireg->iis, ireg->cmsb, ireg->clsb);