Lines Matching refs:dev_priv
99 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
103 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
105 for (i = 0; i < dev_priv->usec_timeout; i++) {
107 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
124 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
128 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
130 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
131 ret = r600_do_wait_for_fifo(dev_priv, 8);
133 ret = r600_do_wait_for_fifo(dev_priv, 16);
136 for (i = 0; i < dev_priv->usec_timeout; i++) {
177 drm_radeon_private_t *dev_priv = dev->dev_private;
178 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
231 drm_radeon_private_t *dev_priv = dev->dev_private;
233 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
234 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
246 drm_radeon_private_t *dev_priv = dev->dev_private;
252 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
253 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
302 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
303 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
304 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
309 static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
324 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
340 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
351 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
354 if (dev_priv->pfp_fw->size != pfp_req_size) {
357 dev_priv->pfp_fw->size, fw_name);
363 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
366 if (dev_priv->me_fw->size != me_req_size) {
369 dev_priv->me_fw->size, fw_name);
380 release_firmware(dev_priv->pfp_fw);
381 dev_priv->pfp_fw = NULL;
382 release_firmware(dev_priv->me_fw);
383 dev_priv->me_fw = NULL;
388 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
393 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
396 r600_do_cp_stop(dev_priv);
408 fw_data = (const __be32 *)dev_priv->me_fw->data;
414 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
428 drm_radeon_private_t *dev_priv = dev->dev_private;
434 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
435 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
471 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
472 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
473 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
478 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
483 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
486 r600_do_cp_stop(dev_priv);
498 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
504 fw_data = (const __be32 *)dev_priv->me_fw->data;
516 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
521 dev_priv->writeback_works = 0;
526 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
530 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
533 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
539 if (tmp < dev_priv->usec_timeout) {
540 dev_priv->writeback_works = 1;
543 dev_priv->writeback_works = 0;
547 dev_priv->writeback_works = 0;
551 if (!dev_priv->writeback_works) {
561 drm_radeon_private_t *dev_priv = dev->dev_private;
586 r600_do_cp_reset(dev_priv);
589 dev_priv->cp_running = 0;
718 drm_radeon_private_t *dev_priv)
742 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
744 dev_priv->r600_max_pipes = 4;
745 dev_priv->r600_max_tile_pipes = 8;
746 dev_priv->r600_max_simds = 4;
747 dev_priv->r600_max_backends = 4;
748 dev_priv->r600_max_gprs = 256;
749 dev_priv->r600_max_threads = 192;
750 dev_priv->r600_max_stack_entries = 256;
751 dev_priv->r600_max_hw_contexts = 8;
752 dev_priv->r600_max_gs_threads = 16;
753 dev_priv->r600_sx_max_export_size = 128;
754 dev_priv->r600_sx_max_export_pos_size = 16;
755 dev_priv->r600_sx_max_export_smx_size = 128;
756 dev_priv->r600_sq_num_cf_insts = 2;
760 dev_priv->r600_max_pipes = 2;
761 dev_priv->r600_max_tile_pipes = 2;
762 dev_priv->r600_max_simds = 3;
763 dev_priv->r600_max_backends = 1;
764 dev_priv->r600_max_gprs = 128;
765 dev_priv->r600_max_threads = 192;
766 dev_priv->r600_max_stack_entries = 128;
767 dev_priv->r600_max_hw_contexts = 8;
768 dev_priv->r600_max_gs_threads = 4;
769 dev_priv->r600_sx_max_export_size = 128;
770 dev_priv->r600_sx_max_export_pos_size = 16;
771 dev_priv->r600_sx_max_export_smx_size = 128;
772 dev_priv->r600_sq_num_cf_insts = 2;
778 dev_priv->r600_max_pipes = 1;
779 dev_priv->r600_max_tile_pipes = 1;
780 dev_priv->r600_max_simds = 2;
781 dev_priv->r600_max_backends = 1;
782 dev_priv->r600_max_gprs = 128;
783 dev_priv->r600_max_threads = 192;
784 dev_priv->r600_max_stack_entries = 128;
785 dev_priv->r600_max_hw_contexts = 4;
786 dev_priv->r600_max_gs_threads = 4;
787 dev_priv->r600_sx_max_export_size = 128;
788 dev_priv->r600_sx_max_export_pos_size = 16;
789 dev_priv->r600_sx_max_export_smx_size = 128;
790 dev_priv->r600_sq_num_cf_insts = 1;
793 dev_priv->r600_max_pipes = 4;
794 dev_priv->r600_max_tile_pipes = 4;
795 dev_priv->r600_max_simds = 4;
796 dev_priv->r600_max_backends = 4;
797 dev_priv->r600_max_gprs = 192;
798 dev_priv->r600_max_threads = 192;
799 dev_priv->r600_max_stack_entries = 256;
800 dev_priv->r600_max_hw_contexts = 8;
801 dev_priv->r600_max_gs_threads = 16;
802 dev_priv->r600_sx_max_export_size = 128;
803 dev_priv->r600_sx_max_export_pos_size = 16;
804 dev_priv->r600_sx_max_export_smx_size = 128;
805 dev_priv->r600_sq_num_cf_insts = 2;
827 switch (dev_priv->r600_max_tile_pipes) {
862 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
866 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
868 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
870 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
881 dev_priv->r600_group_size = 512;
883 dev_priv->r600_group_size = 256;
885 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
887 dev_priv->r600_nbanks = 8;
889 dev_priv->r600_nbanks = 4;
913 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
918 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
922 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
924 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
925 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
926 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
927 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
943 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
944 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
945 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
946 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
951 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
952 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
973 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
987 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
988 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
989 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
990 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
1007 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
1008 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1022 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1045 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1046 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1047 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1048 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1083 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1102 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1134 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1169 static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv,
1211 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1344 drm_radeon_private_t *dev_priv)
1367 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1369 dev_priv->r600_max_pipes = 4;
1370 dev_priv->r600_max_tile_pipes = 8;
1371 dev_priv->r600_max_simds = 10;
1372 dev_priv->r600_max_backends = 4;
1373 dev_priv->r600_max_gprs = 256;
1374 dev_priv->r600_max_threads = 248;
1375 dev_priv->r600_max_stack_entries = 512;
1376 dev_priv->r600_max_hw_contexts = 8;
1377 dev_priv->r600_max_gs_threads = 16 * 2;
1378 dev_priv->r600_sx_max_export_size = 128;
1379 dev_priv->r600_sx_max_export_pos_size = 16;
1380 dev_priv->r600_sx_max_export_smx_size = 112;
1381 dev_priv->r600_sq_num_cf_insts = 2;
1383 dev_priv->r700_sx_num_of_sets = 7;
1384 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1385 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1386 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1389 dev_priv->r600_max_pipes = 2;
1390 dev_priv->r600_max_tile_pipes = 4;
1391 dev_priv->r600_max_simds = 8;
1392 dev_priv->r600_max_backends = 2;
1393 dev_priv->r600_max_gprs = 128;
1394 dev_priv->r600_max_threads = 248;
1395 dev_priv->r600_max_stack_entries = 256;
1396 dev_priv->r600_max_hw_contexts = 8;
1397 dev_priv->r600_max_gs_threads = 16 * 2;
1398 dev_priv->r600_sx_max_export_size = 256;
1399 dev_priv->r600_sx_max_export_pos_size = 32;
1400 dev_priv->r600_sx_max_export_smx_size = 224;
1401 dev_priv->r600_sq_num_cf_insts = 2;
1403 dev_priv->r700_sx_num_of_sets = 7;
1404 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1405 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1406 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1407 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1408 dev_priv->r600_sx_max_export_pos_size -= 16;
1409 dev_priv->r600_sx_max_export_smx_size += 16;
1413 dev_priv->r600_max_pipes = 2;
1414 dev_priv->r600_max_tile_pipes = 2;
1415 dev_priv->r600_max_simds = 2;
1416 dev_priv->r600_max_backends = 1;
1417 dev_priv->r600_max_gprs = 256;
1418 dev_priv->r600_max_threads = 192;
1419 dev_priv->r600_max_stack_entries = 256;
1420 dev_priv->r600_max_hw_contexts = 4;
1421 dev_priv->r600_max_gs_threads = 8 * 2;
1422 dev_priv->r600_sx_max_export_size = 128;
1423 dev_priv->r600_sx_max_export_pos_size = 16;
1424 dev_priv->r600_sx_max_export_smx_size = 112;
1425 dev_priv->r600_sq_num_cf_insts = 1;
1427 dev_priv->r700_sx_num_of_sets = 7;
1428 dev_priv->r700_sc_prim_fifo_size = 0x40;
1429 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1430 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1433 dev_priv->r600_max_pipes = 4;
1434 dev_priv->r600_max_tile_pipes = 4;
1435 dev_priv->r600_max_simds = 8;
1436 dev_priv->r600_max_backends = 4;
1437 dev_priv->r600_max_gprs = 256;
1438 dev_priv->r600_max_threads = 248;
1439 dev_priv->r600_max_stack_entries = 512;
1440 dev_priv->r600_max_hw_contexts = 8;
1441 dev_priv->r600_max_gs_threads = 16 * 2;
1442 dev_priv->r600_sx_max_export_size = 256;
1443 dev_priv->r600_sx_max_export_pos_size = 32;
1444 dev_priv->r600_sx_max_export_smx_size = 224;
1445 dev_priv->r600_sq_num_cf_insts = 2;
1447 dev_priv->r700_sx_num_of_sets = 7;
1448 dev_priv->r700_sc_prim_fifo_size = 0x100;
1449 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1450 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1452 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1453 dev_priv->r600_sx_max_export_pos_size -= 16;
1454 dev_priv->r600_sx_max_export_smx_size += 16;
1477 switch (dev_priv->r600_max_tile_pipes) {
1494 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1515 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1519 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1521 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1523 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)
1526 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv,
1527 dev_priv->r600_max_tile_pipes,
1538 dev_priv->r600_group_size = 512;
1540 dev_priv->r600_group_size = 256;
1542 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
1544 dev_priv->r600_nbanks = 8;
1546 dev_priv->r600_nbanks = 4;
1579 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1582 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740)
1590 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1603 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) {
1609 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1610 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1611 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1613 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1614 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1615 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1627 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1630 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1658 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1664 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1665 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1666 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1668 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1669 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1671 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1672 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1673 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1674 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1675 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1677 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1680 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1681 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1683 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1684 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1686 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1687 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1688 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1689 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1703 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1710 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1723 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1770 drm_radeon_private_t *dev_priv,
1777 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1778 r700_gfx_init(dev, dev_priv);
1780 r600_gfx_init(dev, dev_priv);
1793 (dev_priv->ring.rptr_update_l2qw << 8) |
1794 dev_priv->ring.size_l2qw);
1798 (dev_priv->ring.rptr_update_l2qw << 8) |
1799 dev_priv->ring.size_l2qw);
1812 (dev_priv->ring.rptr_update_l2qw << 8) |
1813 dev_priv->ring.size_l2qw);
1818 (dev_priv->ring.rptr_update_l2qw << 8) |
1819 dev_priv->ring.size_l2qw);
1825 SET_RING_HEAD(dev_priv, 0);
1826 dev_priv->ring.tail = 0;
1829 if (dev_priv->flags & RADEON_IS_AGP) {
1830 rptr_addr = dev_priv->ring_rptr->offset
1832 dev_priv->gart_vm_start;
1836 rptr_addr = dev_priv->ring_rptr->offset
1838 + dev_priv->gart_vm_start;
1848 (dev_priv->ring.rptr_update_l2qw << 8) |
1849 dev_priv->ring.size_l2qw);
1852 (dev_priv->ring.rptr_update_l2qw << 8) |
1853 dev_priv->ring.size_l2qw);
1857 if (dev_priv->flags & RADEON_IS_AGP) {
1858 radeon_write_agp_base(dev_priv, dev->agp->base);
1860 radeon_write_agp_location(dev_priv,
1861 (((dev_priv->gart_vm_start - 1 +
1862 dev_priv->gart_size) & 0xffff0000) |
1863 (dev_priv->gart_vm_start >> 16)));
1865 ring_start = (dev_priv->cp_ring->offset
1867 + dev_priv->gart_vm_start);
1870 ring_start = (dev_priv->cp_ring->offset
1872 + dev_priv->gart_vm_start);
1902 radeon_enable_bm(dev_priv);
1904 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1907 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1910 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1921 r600_do_wait_for_idle(dev_priv);
1927 drm_radeon_private_t *dev_priv = dev->dev_private;
1938 if (dev_priv->flags & RADEON_IS_AGP) {
1939 if (dev_priv->cp_ring != NULL) {
1940 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1941 dev_priv->cp_ring = NULL;
1943 if (dev_priv->ring_rptr != NULL) {
1944 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1945 dev_priv->ring_rptr = NULL;
1955 if (dev_priv->gart_info.bus_addr)
1956 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1958 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1959 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1960 dev_priv->gart_info.addr = NULL;
1964 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1972 drm_radeon_private_t *dev_priv = dev->dev_private;
1977 mutex_init(&dev_priv->cs_mutex);
1980 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1986 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1988 dev_priv->flags &= ~RADEON_IS_AGP;
1993 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1996 dev_priv->flags |= RADEON_IS_AGP;
1999 dev_priv->usec_timeout = init->usec_timeout;
2000 if (dev_priv->usec_timeout < 1 ||
2001 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
2009 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
2010 dev_priv->do_boxes = 0;
2011 dev_priv->cp_mode = init->cp_mode;
2026 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
2030 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
2033 dev_priv->front_offset = init->front_offset;
2034 dev_priv->front_pitch = init->front_pitch;
2035 dev_priv->back_offset = init->back_offset;
2036 dev_priv->back_pitch = init->back_pitch;
2038 dev_priv->ring_offset = init->ring_offset;
2039 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
2040 dev_priv->buffers_offset = init->buffers_offset;
2041 dev_priv->gart_textures_offset = init->gart_textures_offset;
2050 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
2051 if (!dev_priv->cp_ring) {
2056 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
2057 if (!dev_priv->ring_rptr) {
2071 dev_priv->gart_textures =
2073 if (!dev_priv->gart_textures) {
2081 if (dev_priv->flags & RADEON_IS_AGP) {
2082 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
2083 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
2085 if (!dev_priv->cp_ring->handle ||
2086 !dev_priv->ring_rptr->handle ||
2095 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
2096 dev_priv->ring_rptr->handle =
2097 (void *)(unsigned long)dev_priv->ring_rptr->offset;
2101 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2102 dev_priv->cp_ring->handle);
2103 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2104 dev_priv->ring_rptr->handle);
2109 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
2110 dev_priv->fb_size =
2111 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
2112 - dev_priv->fb_location;
2114 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
2115 ((dev_priv->front_offset
2116 + dev_priv->fb_location) >> 10));
2118 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2119 ((dev_priv->back_offset
2120 + dev_priv->fb_location) >> 10));
2122 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2123 ((dev_priv->depth_offset
2124 + dev_priv->fb_location) >> 10));
2126 dev_priv->gart_size = init->gart_size;
2129 if (dev_priv->new_memmap) {
2139 if (dev_priv->flags & RADEON_IS_AGP) {
2142 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2143 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2152 base = dev_priv->fb_location + dev_priv->fb_size;
2153 if (base < dev_priv->fb_location ||
2154 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2155 base = dev_priv->fb_location
2156 - dev_priv->gart_size;
2158 dev_priv->gart_vm_start = base & 0xffc00000u;
2159 if (dev_priv->gart_vm_start != base)
2161 base, dev_priv->gart_vm_start);
2165 if (dev_priv->flags & RADEON_IS_AGP)
2166 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2168 + dev_priv->gart_vm_start);
2171 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2173 + dev_priv->gart_vm_start);
2176 (unsigned int) dev_priv->fb_location,
2177 (unsigned int) dev_priv->fb_size);
2178 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2179 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2180 (unsigned int) dev_priv->gart_vm_start);
2181 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2182 dev_priv->gart_buffers_offset);
2184 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2185 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2187 dev_priv->ring.size = init->ring_size;
2188 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2190 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2191 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2193 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2194 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2196 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2198 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2201 if (dev_priv->flags & RADEON_IS_AGP) {
2205 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2207 if (!dev_priv->pcigart_offset_set) {
2213 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2215 dev_priv->gart_info.bus_addr =
2216 dev_priv->pcigart_offset + dev_priv->fb_location;
2217 dev_priv->gart_info.mapping.offset =
2218 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2219 dev_priv->gart_info.mapping.size =
2220 dev_priv->gart_info.table_size;
2222 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2223 if (!dev_priv->gart_info.mapping.handle) {
2229 dev_priv->gart_info.addr =
2230 dev_priv->gart_info.mapping.handle;
2233 dev_priv->gart_info.addr,
2234 dev_priv->pcigart_offset);
2242 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2248 if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2249 int err = r600_cp_init_microcode(dev_priv);
2256 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2257 r700_cp_load_microcode(dev_priv);
2259 r600_cp_load_microcode(dev_priv);
2261 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2263 dev_priv->last_buf = 0;
2266 r600_test_writeback(dev_priv);
2273 drm_radeon_private_t *dev_priv = dev->dev_private;
2276 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2278 r700_cp_load_microcode(dev_priv);
2281 r600_cp_load_microcode(dev_priv);
2283 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2291 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2307 return r600_do_wait_for_idle(dev_priv);
2312 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2321 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2325 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2336 dev_priv->cp_running = 1;
2340 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2347 SET_RING_HEAD(dev_priv, cur_read_ptr);
2348 dev_priv->ring.tail = cur_read_ptr;
2351 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2361 dev_priv->cp_running = 0;
2367 drm_radeon_private_t *dev_priv = dev->dev_private;
2371 unsigned long offset = (dev_priv->gart_buffers_offset
2403 drm_radeon_private_t *dev_priv = dev->dev_private;
2414 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2420 src_pitch = dev_priv->back_pitch;
2421 dst_pitch = dev_priv->front_pitch;
2422 src = dev_priv->back_offset + dev_priv->fb_location;
2423 dst = dev_priv->front_offset + dev_priv->fb_location;
2425 src_pitch = dev_priv->front_pitch;
2426 dst_pitch = dev_priv->back_pitch;
2427 src = dev_priv->front_offset + dev_priv->fb_location;
2428 dst = dev_priv->back_offset + dev_priv->fb_location;
2466 drm_radeon_private_t *dev_priv = dev->dev_private;
2473 if (!radeon_check_offset(dev_priv, tex->offset)) {
2479 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2522 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2553 static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
2557 *id = radeon_cs_id_get(dev_priv);
2585 drm_radeon_private_t *dev_priv = dev->dev_private;
2597 struct drm_radeon_private *dev_priv = dev->dev_private;
2604 if (dev_priv == NULL) {
2608 family = dev_priv->flags & RADEON_FAMILY_MASK;
2613 mutex_lock(&dev_priv->cs_mutex);
2630 r600_cs_id_emit(dev_priv, &cs_id);
2632 mutex_unlock(&dev_priv->cs_mutex);
2638 struct drm_radeon_private *dev_priv = dev->dev_private;
2640 *npipes = dev_priv->r600_npipes;
2641 *nbanks = dev_priv->r600_nbanks;
2642 *group_size = dev_priv->r600_group_size;