Lines Matching defs:DSR
291 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
377 #define DSR 0x90
1302 /* Wait for modem input (DCD,RI,DSR,CTS) change
1303 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1309 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1381 strcat(stat_buf, "|DSR");
2246 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2363 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2366 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2380 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2383 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2398 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2416 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2419 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
3010 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4136 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4162 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4187 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4237 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4255 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4281 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4762 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
5500 /* called to periodically check the DSR/RI modem signal input status
5514 /* check for DSR/RI state change */