Lines Matching refs:port_mmio
250 void __iomem *port_mmio = ahci_port_base(ap);
252 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
521 void __iomem *port_mmio = ahci_port_base(link->ap);
525 *val = readl(port_mmio + offset);
533 void __iomem *port_mmio = ahci_port_base(link->ap);
537 writel(val, port_mmio + offset);
545 void __iomem *port_mmio = ahci_port_base(ap);
549 tmp = readl(port_mmio + PORT_CMD);
551 writel(tmp, port_mmio + PORT_CMD);
552 readl(port_mmio + PORT_CMD); /* flush */
558 void __iomem *port_mmio = ahci_port_base(ap);
561 tmp = readl(port_mmio + PORT_CMD);
569 writel(tmp, port_mmio + PORT_CMD);
572 tmp = ata_wait_register(port_mmio + PORT_CMD,
583 void __iomem *port_mmio = ahci_port_base(ap);
591 port_mmio + PORT_LST_ADDR_HI);
592 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
596 port_mmio + PORT_FIS_ADDR_HI);
597 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
600 tmp = readl(port_mmio + PORT_CMD);
602 writel(tmp, port_mmio + PORT_CMD);
605 readl(port_mmio + PORT_CMD);
610 void __iomem *port_mmio = ahci_port_base(ap);
614 tmp = readl(port_mmio + PORT_CMD);
616 writel(tmp, port_mmio + PORT_CMD);
619 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
630 void __iomem *port_mmio = ahci_port_base(ap);
633 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
638 writel(cmd, port_mmio + PORT_CMD);
642 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
648 void __iomem *port_mmio = ahci_port_base(ap);
654 cmd = readl(port_mmio + PORT_CMD);
664 writel(cmd, port_mmio + PORT_CMD);
665 cmd = readl(port_mmio + PORT_CMD);
671 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
686 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
698 void __iomem *port_mmio = ahci_port_base(ap);
737 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
747 cmd = readl(port_mmio + PORT_CMD);
762 writel(cmd, port_mmio + PORT_CMD);
763 cmd = readl(port_mmio + PORT_CMD);
773 void __iomem *port_mmio = ahci_port_base(ap);
780 scontrol = readl(port_mmio + PORT_SCR_CTL);
782 writel(scontrol, port_mmio + PORT_SCR_CTL);
785 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
787 writel(cmd, port_mmio + PORT_CMD);
1132 void __iomem *port_mmio)
1144 tmp = readl(port_mmio + PORT_SCR_ERR);
1146 writel(tmp, port_mmio + PORT_SCR_ERR);
1149 tmp = readl(port_mmio + PORT_IRQ_STAT);
1152 writel(tmp, port_mmio + PORT_IRQ_STAT);
1162 void __iomem *port_mmio;
1168 port_mmio = ahci_port_base(ap);
1172 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1196 void __iomem *port_mmio = ahci_port_base(ap);
1200 tmp = readl(port_mmio + PORT_SIG);
1224 void __iomem *port_mmio = ahci_port_base(ap);
1226 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1250 tmp = readl(port_mmio + PORT_CMD);
1252 writel(tmp, port_mmio + PORT_CMD);
1255 tmp = ata_wait_register(port_mmio + PORT_CMD,
1273 void __iomem *port_mmio = ahci_port_base(ap);
1282 writel(1, port_mmio + PORT_CMD_ISSUE);
1285 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1292 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1362 void __iomem *port_mmio = ahci_port_base(link->ap);
1363 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1415 void __iomem *port_mmio = ahci_port_base(ap);
1421 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1427 writel(new_tmp, port_mmio + PORT_CMD);
1428 readl(port_mmio + PORT_CMD); /* flush */
1507 void __iomem *port_mmio = ahci_port_base(ap);
1508 u32 fbs = readl(port_mmio + PORT_FBS);
1517 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1518 fbs = readl(port_mmio + PORT_FBS);
1521 fbs = readl(port_mmio + PORT_FBS);
1542 void __iomem *port_mmio = ahci_port_base(ap);
1543 u32 fbs = readl(port_mmio + PORT_FBS);
1643 void __iomem *port_mmio = ahci_port_base(ap);
1651 status = readl(port_mmio + PORT_IRQ_STAT);
1652 writel(status, port_mmio + PORT_IRQ_STAT);
1704 qc_active = readl(port_mmio + PORT_SCR_ACT);
1705 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1710 qc_active = readl(port_mmio + PORT_SCR_ACT);
1712 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1790 void __iomem *port_mmio = ahci_port_base(ap);
1800 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1803 u32 fbs = readl(port_mmio + PORT_FBS);
1806 writel(fbs, port_mmio + PORT_FBS);
1810 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1843 void __iomem *port_mmio = ahci_port_base(ap);
1846 writel(0, port_mmio + PORT_IRQ_MASK);
1853 void __iomem *port_mmio = ahci_port_base(ap);
1858 tmp = readl(port_mmio + PORT_IRQ_STAT);
1859 writel(tmp, port_mmio + PORT_IRQ_STAT);
1863 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1892 void __iomem *port_mmio = ahci_port_base(ap);
1899 fbs = readl(port_mmio + PORT_FBS);
1910 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1911 fbs = readl(port_mmio + PORT_FBS);
1925 void __iomem *port_mmio = ahci_port_base(ap);
1932 fbs = readl(port_mmio + PORT_FBS);
1942 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1943 fbs = readl(port_mmio + PORT_FBS);
1956 void __iomem *port_mmio = ahci_port_base(ap);
1960 cmd = readl(port_mmio + PORT_CMD);
1962 writel(cmd, port_mmio + PORT_CMD);
1967 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1972 void __iomem *port_mmio = ahci_port_base(ap);
1978 cmd = readl(port_mmio + PORT_CMD);
1980 writel(cmd, port_mmio + PORT_CMD);
1983 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2032 void __iomem *port_mmio = ahci_port_base(ap);
2033 u32 cmd = readl(port_mmio + PORT_CMD);